发表机构
Columbia University; Inner Mongolia University of Science and Technology; New York Unversity（哥伦比亚大学; 内蒙古科技大学; 纽约大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本研究利用GPT-4o辅助LDO稳压器全流程设计，并通过电磁分析评估三种电感布局方案，发现反馈路径外电感可保持稳定性并抑制高频干扰。
AI 中文摘要
本工作系统评估了生成式大语言模型（LLM），特别是GPT-4o，在支持低压差（LDO）线性稳压器全设计、仿真和优化工作流程中的能力。研究涵盖四个核心设计阶段：设计前规格映射、晶体管级电路拓扑生成、SPICE仿真指导以及仿真后性能微调，并扩展研究了磁性电感元件在LDO信号路径中的集成。GPT-4o自主提出了一种采用薄氧化物MOS晶体管的单级差分对误差放大器架构，为PMOS导通元件提供了尺寸指导，并推荐了无源补偿网络以确保闭环稳定性。LDO测试平台遵循低压便携式电子设备规格：输入范围为0.8-1.2 V，可调输出为0.7-1.1 V，最大负载电流为250 mA，可集成输出电容低于10 nF。瞬态和小信号AC SPICE仿真验证了LLM辅助电路实现，量化了通过补偿电容实现的建立时间缩减，并验证了在工作带宽内具有足够的相位裕度。一个关键的新扩展探索了三种不同的电感布局方案：输入侧电源滤波、环路外LC输出滤波以及嵌入反馈分压器内的感性负载，这些方案基于麦克斯韦电动力学原理和MOSFET小信号器件物理。比较性Bode图和输出阻抗分析表明，插入反馈路径内部的电感会引入谐振复极点、严重的增益峰值和相位裕度下降，而放置在反馈检测抽头外部的电感则在抑制高频电磁干扰的同时保持了稳压器的稳定性。
英文摘要
This work systematically evaluates the capability of generative large language models (LLMs), specifically GPT-4o, to support the full design, simulation, and optimization workflow of low-dropout (LDO) linear voltage regulators. The study covers four core design phases: pre-design specification mapping, transistor-level circuit topology generation, SPICE simulation guidance, and post-simulation performance fine-tuning, with an extended investigation into the integration of magnetic inductive components within the LDO signal path. GPT-4o autonomously proposes a single-stage differential-pair error amplifier architecture with thin-oxide MOS transistors, provides sizing guidance for the PMOS pass element, and recommends passive compensation networks to secure closed-loop stability. The LDO testbench adheres to low-voltage portable electronics specifications: an input range of 0.8-1.2 V, tunable 0.7-1.1 V output, maximum 250 mA load current, and integrable output capacitance below 10 nF. Transient and small-signal AC SPICE simulations validate LLM-assisted circuit implementations, quantifying settling time reduction via compensation capacitors and verifying adequate phase margin across operating bandwidth. A key novel extension explores three distinct inductor placement schemes, input-side supply filtering, out-of-loop LC output filtering, and inductive loading embedded within the feedback divider, rooted in Maxwell's electrodynamic principles and MOSFET small-signal device physics. Comparative Bode and output impedance analysis reveals that inductors inserted inside the feedback path introduce resonant complex poles, severe gain peaking, and degraded phase margin, while inductors placed external to the feedback sensing tap preserve regulator stability while suppressing high-frequency electromagnetic interference.
