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AgenticSizing:一种基于大语言模型的多智能体模拟电路尺寸优化框架

AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing

Yijia Hao, Pratibha Verma, Dongxu Guo, Cristian Sestito, Michael O'Boyle, Christos-Savvas Bouganis, Themis Prodromakis

arXiv 2609.25873首次发表:更新:

发表机构

The University of Edinburgh; Indian Institute of Technology Indore; Imperial College London(爱丁堡大学; 印度理工学院印多尔分校; 帝国理工学院)

机构由 AI 辅助整理,请以论文原文为准。

AI 中文总结

提出一种基于大语言模型的多智能体框架,通过拓扑分解、知识提取和角色专化智能体协作,实现复杂模拟电路尺寸优化,在LDO基准上以60%成功率超越经典优化器。

AI 中文摘要

由于设计空间庞大、性能权衡强烈以及先进工艺下电路复杂度的不断增加,模拟电路尺寸优化仍然是一项具有挑战性且耗时的任务。尽管近期基于大语言模型(LLM)的方法在提高样本效率和可解释性方面显示出潜力,但现有方法往往缺乏对电路拓扑的显式理解,且主要针对相对简单的模拟构建模块进行评估。本文提出了一种用于复杂模拟电路尺寸优化的多智能体LLM框架。该框架首先分析电路拓扑,将网表分解为功能模块和子结构,并提取轻量级设计知识以供复用。基于提取的拓扑和知识,一个规划器协调多个角色专化的尺寸优化智能体,以更新设计变量并实现全局性能指标。该工作流程模拟了专家模拟设计团队的协作过程,提供了一种结构化、可解释且由仿真驱动的优化流程。该框架在八个电路上进行了验证,其中最大的设计包含多达55个晶体管和60个尺寸变量。值得注意的是,在LDO基准测试中,所提方法以平均83次迭代实现了60%的成功率,而经典优化器未能找到可行解。此外,消融研究表明,拓扑理解、设计知识注入和智能体专化提供了互补的益处。源代码已公开以支持可复现性。

英文摘要

Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies. Although recent large language model (LLM)-based methods show promise in improving sample efficiency and interpretability, existing approaches often lack explicit circuit-topology understanding and are mainly evaluated on relatively simple analog building blocks. This paper presents a multi-agent LLM-based framework for complex analog circuit sizing. The proposed framework first analyzes the circuit topology and decomposes the netlist into functional blocks and substructures. It also extracts lightweight design knowledge for reuse. Based on the extracted topology and knowledge, a planner coordinates multiple role-specialized sizing agents to update design variables and achieve global performance specifications. This workflow mimics the collaborative process of an expert analog design team and provides a structured, interpretable, and simulation-driven optimization procedure. The framework was validated on eight circuits, with the largest design containing up to 55 transistors and 60 sizing variables. Notably, for the LDO benchmark, the proposed method achieved a 60\% success rate with an average of 83 iterations, where classical optimizers failed to find feasible solutions. Further, ablation studies demonstrate that topology understanding, design-knowledge infusion, and agent specialization provide complementary benefits. The source code is available to support reproducibility.

论文原文

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