发表机构
Northeastern University（东北大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
FASTAR提出一种基于FPGA的FRI协议加速器，采用约束驱动设计和HLS参数化模块，自动生成适配不同FPGA资源的硬件实现，以提升后量子零知识证明的能效和可部署性。
AI 中文摘要
零知识证明（ZKP）使证明者能够以密码学方式向验证者证明某个陈述的有效性，同时不泄露任何底层秘密，构成了可验证计算的基础原语。ZKP领域正经历从经典zk-SNARK（如Groth16，依赖可信设置且易受量子攻击）向透明、后量子构造（如zk-STARK）的根本性转变。这些系统仅依赖抗碰撞哈希函数实现后量子安全性，但代价是巨大的计算开销。特别是，快速Reed-Solomon交互式预言机邻近证明（FRI）协议主导了证明者复杂度，产生海量数据、重复的Merkle树承诺以及不规则的内存访问模式，限制了通用处理器上的性能和能效。为解决这些挑战，本工作提出FASTAR，一种新颖的基于FPGA的FRI协议加速器。与在昂贵的ASIC工艺节点上追求固定高性能内核的加速器不同，FASTAR采用约束驱动设计方法论。我们的框架使用高级综合（HLS）实现，由完全参数化的构建模块组成，涵盖FRI的主要阶段，包括多项式求值、递归分割与折叠以及Merkle树构建。根据用户提供的板卡规格，FASTAR自动生成针对目标FPGA资源和内存约束定制的硬件实现，无需手动重新设计即可在广泛平台上部署。
英文摘要
Zero-Knowledge Proofs (ZKPs) enable a prover to cryptographically convince a verifier of the validity of a statement without revealing any underlying secrets, forming a foundational primitive for verifiable computation. The ZKP landscape is undergoing a fundamental shift from classic zk-SNARKs such as Groth16, which rely on trusted setup and are vulnerable to quantum adversaries, toward transparent, post-quantum constructions such as zk-STARK. These systems achieve post-quantum security by relying solely on collision-resistant hash functions, however, at the cost of substantial computational overhead. In particular, the Fast Reed--Solomon Interactive Oracle Proof of Proximity (FRI) protocol dominates prover complexity, generating massive data volumes, repeated Merkle-tree commitments, and irregular memory access patterns that limit performance and energy efficiency on general-purpose processors. To address these challenges, this work proposes FASTAR, a novel FPGA-based accelerator for the FRI protocol. Unlike accelerators that pursue fixed high-performance kernels on expensive ASIC process nodes, FASTAR adopts a constraint-driven design methodology. Our framework is implemented with High-Level Synthesis (HLS) and composed of fully parameterizable building blocks for the major stages of FRI, including polynomial evaluation, recursive split-and-fold, and Merkle-tree construction. From user-provided board specifications, FASTAR automatically generates hardware implementations tailored to the resource and memory constraints of the target FPGA, enabling deployment across a wide range of platforms without manual redesign.
Comments9 pages, 2 figures, 4 tables; ICCAD 2026
