发表机构
University of Electronic Science and Technology of China（电子科技大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文提出电路-架构-训练协同设计框架，利用SA再生检测模拟相似性，在CIM中激进跳过SAR比较，实现48.19%比较减少和27.18%参考ADC能耗降低，准确率损失仅1.1%。
AI 中文摘要
本文提出一种电路-架构-训练协同设计框架，利用感测放大器（SA）的再生特性检测模拟输出相似性，以减少存内计算（CIM）系统中的SAR比较次数。硬件感知训练结合了电路表征的SA扰动及由前缀重用引起的编码误差，从而实现激进的比较跳变。该检测器通过55-nm CMOS原理图仿真进行表征，并在基于ISAAC的W4A4 CIM模型上对WRN-28-10、ResNet20和DeiT进行系统级评估。在WRN-28-10上，所提方法实现了77.3%的Top-1准确率（W4A4基线为78.4%），同时在被评估层中减少了48.19%的SAR比较。能量预算分析估计，在扣除检测器开销后，参考ADC能量减少27.18%，每次转换剩余0.52 pJ以容纳额外的控制和外围成本。
英文摘要
This work presents a circuit-architecture-training co-design framework that exploits sense-amplifier (SA) regeneration to detect analog-output similarity and reduce SAR comparisons in compute-in-memory (CIM) systems. Hardware-aware training incorporates circuit-characterized SA disturbance and encoding errors caused by prefix reuse, enabling aggressive comparison skipping. The detector is characterized through 55-nm CMOS schematic simulations, with system-level evaluation on WRN-28-10, ResNet20, and DeiT using an ISAAC-based W4A4 CIM model. On WRN-28-10, the proposed approach achieves 77.3% Top-1 accuracy (W4A4 baseline: 78.4%) while reducing SAR comparisons by 48.19% across the evaluated layers. Energy-budget analysis estimates a 27.18% reduction in reference ADC energy after detector overhead, leaving 0.52 pJ per conversion to accommodate additional control and peripheral costs.
Comments5 figures, 2 tables. Submitted to the 2027 IEEE International Symposium on Circuits and Systems (ISCAS 2027)
