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arXiv 2609.22743cs.AR

TEMPO:一种基于标签的高效内存排序框架

TEMPO: A Tag-Based Framework for Efficient Memory Ordering

  • Georgia Institute of Technology(佐治亚理工学院)
  • Arm(安谋)
  • NVIDIA(英伟达)
  • Samsung Electronics(三星电子)

机构由 AI 辅助整理,请以论文原文为准。

Pranith Kumar, Prasun Gera, Hyojong Kim, Chulhyung Park, Hyesoon Kim

AI总结:

TEMPO提出基于标签的框架,通过轻量级标签和分解强制机制,精确实现弱内存排序,消除不必要的退役串行化和推测加载清除,提升性能并降低开销。

AI中文摘要:

弱内存处理器依赖排序指令来保证正确性,然而传统实现往往比内存模型要求的更保守地强制执行这些指令。这种过度强制表现为排序指令处由排空引起的停顿(retirement stalls)以及推测加载的保守清除/重放,抑制了合法执行并降低了吞吐量。我们提出了TEMPO,一种用于精确微架构实现排序指令的基于标签的框架。TEMPO为指令分配轻量级排序标签,并将强制操作分解为退役时谓词和完成时存储排序,使核心能够在无需保守退役串行化的情况下强制执行所需排序。TEMPO消除了排序指令处不必要的退役串行化以及推测加载的清除/重放。在我们的评估中,TEMPO在原生四线程工作负载上将几何平均归一化执行周期减少了7.9%,并在用于跨ISA执行(例如x86-on-Arm)的插桩SPEC2017动态二进制翻译(DBT)代理上将几何平均IPC提高了15.9%,而每核心仅增加262字节。

英文摘要:

Weak-memory processors rely on ordering instructions for correctness, yet conventional implementations often enforce them more conservatively than the memory model requires. This over-enforcement manifests as drain-induced retirement stalls at ordering instructions and conservative squash/replay of speculative loads, suppressing legal executions and reducing throughput. We present TEMPO, a tag-based framework for precise micro-architectural implementation of ordering instructions. TEMPO assigns lightweight ordering tags to instructions and decomposes enforcement across retirement-time predicates and completion-time store ordering, allowing the core to enforce required ordering without conservative retirement serialization. TEMPO eliminates unnecessary retirement serialization at ordering instructions and speculative-load squash/replay. In our evaluation, TEMPO reduces geometric-mean normalized execution cycles by 7.9% on native four-thread workloads and improves geometric-mean IPC by 15.9% on an instrumented SPEC2017 dynamic binary translation (DBT) proxy for cross- ISA execution (e.g., x86-on-Arm), while adding only 262 bytes per core.

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