发表机构
Global College, Shanghai Jiao Tong University; Department of Mathematics and Computer Science, Eindhoven University of Technology（上海交通大学全球学院; 埃因霍温理工大学数学与计算机科学系）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文提出将近似逻辑综合集成到近似高层综合流程中，以扩展设计空间并生成更高质量的近似电路，实验显示在相同误差界限下硬件成本平均降低11%。
AI 中文摘要
近似高层综合（HLS）和近似逻辑综合（ALS）是生成近似电路的两种技术，它们在不同粒度上操作。近似HLS通常修改控制与数据流图中的指令，而ALS则修改门级网表中的门和互连。缺乏结合这两种技术的统一框架限制了联合优化的潜力。为弥合这一差距，我们提出将ALS集成到近似HLS的流程中。这种集成通过引入由ALS产生的细粒度近似，扩展了近似HLS的设计空间，从而生成更高质量的近似电路。实验结果表明，在相同误差界限下，与最先进的方法相比，我们的方法平均降低了11%的硬件成本。
英文摘要
Approximate high-level synthesis (HLS) and approximate logic synthesis (ALS) are two techniques for generating approximate circuits. They operate at different granularities. Approximate HLS typically modifies instructions in a control and data flow graph, whereas ALS modifies gates and interconnects in a gate-level netlist. The absence of a unified framework combining these techniques limits the potential for joint optimization. To bridge this gap, we propose to integrate ALS into the flow of approximate HLS. This integration expands the design space of approximate HLS by introducing fine-grained approximation induced by ALS, thereby generating approximate circuits with higher quality. Experimental results show that under the same error bound, our method reduces the hardware cost by 11% on average compared to the state-of-the-art methods.
CommentsAccepted at 2026 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
