离散傅里叶变换的内存计算实现的设计空间探索
Design Space Exploration of In-Memory Computing Implementations for Discrete Fourier Transform
- Lund University（隆德大学）
- Ericsson Research（爱立信研究院）
机构由 AI 辅助整理，请以论文原文为准。
AI总结：
本文提出一种硬件感知设计框架，以DFT为案例探索内存计算实现，新映射方案降低53%能耗，并对比RRAM与FTJ技术，为节能边缘加速器提供路径。
AI中文摘要：
尽管基于忆阻器的内存计算（IMC）已被广泛研究用于类脑神经形态工作负载，但在经典数字信号处理（DSP）领域，针对不同系统参数下其能量、延迟和信噪比（SNR）权衡的系统性评估仍然稀缺。为弥补这一空白，本文引入了一个全面的硬件感知设计框架，用于将算法工作负载系统地映射到IMC架构上，并以离散傅里叶变换（DFT）作为案例研究。针对5G正交频分复用（OFDM）系统中DFT加速器的严格性能要求，我们提出了一种新颖的映射方案，与传统映射技术相比，每次计算的能耗降低了53%。此外，我们对比研究了具有相同可编程状态数量但电导范围不同的电阻式随机存取存储器（RRAM）和铁电隧道结（FTJ）技术，展示了器件信息感知的架构协同设计的重要性。通过弥合新兴IMC架构与刚性DSP约束之间的差距，这项工作为未来无线通信系统的节能边缘加速器提供了一条路径。
英文摘要：
Although memristor-based in-memory computing (IMC) has been widely investigated for brain-inspired neuromorphic workloads, systematic evaluations of its energy, latency, and signal-to-noise ratio (SNR) trade-offs across diverse system parameters remain scarce for classical digital signal processing (DSP). To address this gap, this paper introduces a comprehensive hardware-aware design framework for systematically mapping algorithmic workloads onto IMC architectures, using the discrete Fourier transform (DFT) as a case study. Tailored to the stringent performance requirements of a DFT accelerator for 5G orthogonal frequency-division multiplexing (OFDM) systems, we propose a novel mapping scheme that reduces energy consumption per computation by 53% compared with conventional mapping techniques. Additionally, we present a comparative study of resistive random-access memory (RRAM) and ferroelectric tunnel junction (FTJ) technologies with identical numbers of programmable states but distinct conductance ranges, demonstrating the importance of device-informed architectural co-design. By bridging the gap between emerging IMC architectures and rigid DSP constraints, this work provides a pathway toward energy-efficient edge accelerators for future wireless communication systems.
