PlaceReasoner-Beta：推理驱动的宏单元布局与基准测试

中文摘要 AI 辅助

自动化宏单元布局仍然是VLSI物理设计中的一个基本挑战。尽管经过数十年的研究，现有方法主要优化手工设计的代理目标，如估计线长，并且通常通过一次性数值优化来生成布局，这限制了它们在统一循环中整合视觉布局上下文、编码的设计专业知识和下游物理设计反馈的能力。我们提出了PlaceReasoner-Beta，一个验证器引导的多智能体框架，将宏单元布局重新定义为闭环推理问题，而非黑盒优化。视觉语言模型（VLM）规划器根据版图图像、宏单元规格和连接结构生成候选布局；几何验证器强制执行物理合法性和专家布局原则；物理验证器利用早期实现反馈优化候选方案；布线后优化器使用最终PPA进一步改进有前景的布局。为了实现可复现的评估，我们引入了PlaceReasoner-Bench，一个完全开放、端到端的基准测试，基于开放的RTL设计、EDA工具和技术库构建。它包含8个设计，每个设计有两种宽高比，共产生16个任务，具有固定的版图和I/O分配，因此不同方法仅在宏单元位置和方向上有差异，并使用布线后的PPA和DRC而非布线前代理指标进行评估。在整个基准测试中，PlaceReasoner-Beta在所有方形任务中实现了DRC干净方法中的最佳时序，相对于经典基线场，在1:1和2:1宽高比下分别将布线后TNS降低了61.2%和53.0%。尽管从未显式优化布线线长，它在大多数设计上缩短了布线线长，这表明在物理设计反馈下对空间结构进行推理可以超越代理目标优化，提高端到端布局质量。

英文摘要

Automated macro placement remains a fundamental challenge in VLSI physical design. Despite decades of research, existing approaches predominantly optimize hand-crafted proxy objectives, such as estimated wirelength, and typically produce placements through one-shot numerical optimization, limiting their ability to incorporate visual layout context, codified design expertise, and downstream physical-design feedback in a unified loop. We present PlaceReasoner-Beta, a verifier-guided multi-agent framework that reformulates macro placement as a closed-loop reasoning problem rather than black-box optimization. A vision-language model (VLM) planner generates candidate placements from the floorplan image, macro specifications, and connectivity structure; a geometric verifier enforces physical legality and expert placement principles; a physical verifier refines candidates using early implementation feedback; and a post-route optimizer further improves promising layouts using final PPA. To enable reproducible evaluation, we introduce PlaceReasoner-Bench, a fully open end-to-end benchmark built from open RTL designs, EDA tools, and technology libraries. It comprises 8 designs at two aspect ratios, yielding 16 tasks with fixed floorplans and I/O assignments, so methods differ only in macro positions and orientations and are evaluated using routed PPA and DRC rather than pre-route proxies. Across the benchmark, PlaceReasoner-Beta achieves the best timing among DRC-clean methods on all square tasks, reducing post-route TNS by 61.2% at 1:1 and 53.0% at 2:1 relative to the classical baseline field. It also shortens routed wirelength on most designs despite never explicitly optimizing it, demonstrating that reasoning over spatial structure under physical-design feedback can improve end-to-end layout quality beyond proxy-objective optimization.

发表机构

• The George Washington University（乔治·华盛顿大学）
• University of California, Los Angeles（加州大学洛杉矶分校）
• Brown University（布朗大学）
• Brookhaven National Laboratory（布鲁克海文国家实验室）
• NVIDIA Corp（英伟达公司）
• UT Austin（德克萨斯大学奥斯汀分校）

机构由 AI 辅助整理，请以论文原文为准。