通过界面电荷动力学调控铁电Hf0.5Zr0.5O2-Al2O3异质结构中的矫顽场
Tuning the Coercive Field in Ferroelectric Hf0.5Zr0.5O2-Al2O3 Heterostructures via Interfacial Charge Dynamics
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中文总结 AI 辅助
本研究通过实验和相场模拟揭示，HZO-Al2O3异质结构中氧空位引起的界面电荷隧穿产生内偏置，从而调控矫顽场并增大存储窗口，将缺陷从有害因素转变为可工程利用的设计参数。
中文摘要 AI 辅助
将介电层插入铁电Hf0.5Zr0.5O2（HZO）薄膜中，可使存储窗口（MW）增大，其增幅超出了介电常数所能解释的范围。确定这些MW改善背后的物理机制，对于充分发挥HZO FeNAND的潜力至关重要。在此，我们表明MW的改善源于层间界面处氧空位所实现的界面电荷动力学。X射线光电子能谱（XPS）刻蚀实验表明，界面处非化学计量比增加，氧空位增加了2.3倍。偏振依赖XPS和一级反转曲线（FORC）表明，界面缺陷态之间的隧穿引起了0.56 MV/cm的双向内偏置。缺陷的影响通过相场模拟（PFM）得到进一步证实，该模拟仅在缺陷密度和隧穿势垒高度与实验一致时，才能重现矫顽场、FORC和内偏置，定量捕获了0.55 MV/cm的内电场。随后，利用相场模型模拟了36个具有不同电荷密度和介电层厚度的器件，为层间HZO存储窗口的进一步改善提供了预测框架。这些发现将铁电HZO中缺陷的角色从有害重新定义为可工程调控，并为如何调整铁电器件架构以改善存储器性能提供了关键见解。
英文摘要
Interleaving dielectric layers into ferroelectric Hf0.5Zr0.5O2 (HZO) films increases the memory window (MW) beyond what is accounted for by the dielectric constants. Determining the physical mechanisms behind these MW improvements is critical to reaching the full potential of HZO FeNAND. Here, we show that MW improvements stem from the interfacial charge dynamics enabled by oxygen vacancies at the interlayer interface. X-ray photoelectron spectroscopy(XPS) etching experiments demonstrate increased off-stoichiometry at the interface, with a 2.3x increase in oxygen vacancies. Polarization-dependent XPS and first-order reversal curves(FORC) show that tunneling between interfacial defect states causes a bidirectional internal bias of 0.56MV/cm. The impact of defects is further corroborated through phase-field modeling(PFM), which only recreates the coercive fields, FORC, and internal bias for defect densities and tunneling barrier heights that are consistent with experiment, quantitatively capturing an internal electric field of 0.55 MV/cm. The phase field models are then used to simulate 36 devices with varied charge densities and dielectric thickness to provide a predictive framework for further improvements in the MW of interlayer HZO. These findings redefine the role of defects in ferroelectric HZO from deleterious to engineerable and provide critical insights into how to tune ferroelectric device architectures for improved memory.
发表机构
- School of Materials Science and Engineering, Georgia Institute of Technology（佐治亚理工学院材料科学与工程学系）
- School of Electrical and Computer Engineering, Georgia Institute of Technology（佐治亚理工学院电气与计算机工程学系）
- Center for Nanophase Materials Sciences, Oak Ridge National Laboratory（橡树岭国家实验室纳米相材料科学中心）
- The Institute for Matter and Systems, Georgia Institute of Technology（佐治亚理工学院物质系统研究所）
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