发表机构
University of Texas at Arlington; Manning College of Information and Computer Sciences, University of Massachusetts Amherst; Department of Electrical and Computer Engineering, University of Maryland College Park（阿灵顿得克萨斯大学; 马萨诸塞大学阿姆赫斯特分校曼宁信息学与计算机科学学院; 马里兰大学帕克分校电气与计算机工程系）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本研究提出混合中继链架构，结合两类存储器优势，通过蒙特卡洛模拟证明其在端到端纠缠分发速率上优于纯架构，并开发了改进的交换策略以减少存储时间。
AI 中文摘要
长距离纠缠分发需要纠错协议来补偿量子存储器中量子比特的退相干以及纠缠交换过程中引入的噪声。我们认为，具有纠错能力的中继链应利用不止一种物理平台，将不同量子存储器技术的互补优势结合到单一的混合中继架构中。这种架构的一个重要组成部分是混合中继，它结合了类型1存储器（以快速纠缠生成速率和适合多路复用为特征）和类型2存储器（提供长相干时间和低双量子比特门错误率）。考虑到混合节点的资源密集型特性，我们提出并分析了中继链，其中只有一部分节点需要是混合的，而其余节点是更简单的第一代中继器，没有纠错能力。通过对基于三量子比特相位翻转重复码、$[[7,1,3]]$ Steane码和$[[9,1,3]]$ Shor码的容错编码中继链协议进行详细的蒙特卡洛模拟，我们证明了这些混合架构在端到端纠缠分发速率方面优于基于单一存储器平台的纯架构。在我们的研究中，我们开发了架构的完整电路级噪声模型，并检查了两个平台之间不完美接口对混合架构的影响。我们还开发了一种修改版的“尽快交换”策略并结合多路复用，更适合我们的架构，其中一些节点执行纠错而其他节点不执行。与先前在编码中继链中考虑的交换策略相比，这种修改后的策略显著减少了存储器量子比特中的信息存储时间。
英文摘要
Long-distance entanglement distribution requires error correction protocols to compensate for qubit decoherence in quantum memories and noise introduced during entanglement swapping. We argue that repeater chains with error-correction capabilities should exploit more than one physical platform, combining the complementary strengths of different quantum memory technologies into a single hybrid repeater architecture. An important constituent of such an architecture is a hybrid repeater which combines type-1 memories, characterized by fast entanglement generation rates and suitability for multiplexing, and type-2 memories that offer long coherence times and low two-qubit gate error rates. Taking the resource-intensive nature of hybrid nodes into account, we propose and analyze repeater chains in which only a subset of nodes need to be hybrid, while the remaining nodes are simpler first-generation repeaters with no error-correction capability. Through detailed Monte Carlo simulations of fault-tolerant encoded repeater chain protocols based on the three-qubit phase-flip repetition code, the $[[7,1,3]]$ Steane code, and the $[[9,1,3]]$ Shor code, we demonstrate that these hybrid architectures outperform pure architectures based on a single memory platform in terms of end-to-end entanglement distribution rate. In our study we develop a full circuit-level noise model of our architectures and examine the impact of an imperfect interface between the two platforms on our hybrid architecture. We also develop a modified version of the swap-as-soon-as-possible policy with multiplexing, more suited to our architecture where some nodes perform error-correction while others do not. This modified policy significantly reduces the information storage time in memory qubits relative to the previously considered swap policies in encoded repeater chains.
Comments28 pages main text (plus 14 pages Appendix), 12 figures. Comments are welcome
