发表机构
Microsoft; ETH Zürich（微软; 苏黎世联邦理工学院）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文提出量子计算机在系统规模上应遵循经典异构加速器原则，以成本-性能为核心，通过逻辑抽象和专用硬件设计可扩展QPU架构，并借鉴经典计算与网络实践。
AI 中文摘要
量子计算机在技术上新颖且不寻常，但在系统规模上，其工程应遵循许多支配经典异构加速器的相同原则。本文认为，实用规模的量子架构主要是一个跨耦合量子-经典系统的成本-性能问题，由此提出了可扩展量子处理单元（QPU）设计的蓝图。我们的架构蓝图围绕清晰的逻辑抽象组织，将物理量子比特模态的细节和复杂性隐藏在指令集架构（ISA）边界之下，并积极地对重复功能进行专门化，以最小化实用规模量子计算的成本。其通过用于控制、读出和量子纠错（QEC）的专用本地硬件实现的低层实现，与高性能网络栈的架构非常相似。我们的主要见解之一是，设计原则及由此产生的架构紧密遵循经典计算和网络领域的成熟实践。
英文摘要
Quantum computers are technologically novel and unusual, but at system scale they should be engineered using many of the same principles that govern classical heterogeneous accelerators. This paper argues that utility-scale quantum architecture is primarily a cost-performance problem across a coupled quantum-classical system, leading to a blueprint for scalable quantum processing unit (QPU) design. Our architecture blueprint is organized around clean logical abstractions, hiding details and complexity of physical qubit modalities below the instruction set architecture (ISA) boundary, and specializes recurring functions aggressively to minimize the cost for utility scale quantum computations. Its low-level implementation through specialized local hardware for control, readout, and quantum error correction (QEC) closely resembles the architecture of high-performance network stacks. One of our main insights is that the design principles and the resulting architecture closely follow established practice from classical computing and networking.
