SpecReuse：面向FPGA高效视觉GNN推理的谱图复用
SpecReuse: Spectral Graph Reuse for Efficient Vision GNN Inference on FPGAs
- University of Southern California（南加州大学）
机构由 AI 辅助整理，请以论文原文为准。
AI总结：
针对FPGA上视觉GNN推理中动态图构建的性能瓶颈，提出SpecReuse算法与加速器，通过谱描述符漂移检测实现图复用，实现最高2.69倍加速和约58-65%能耗降低。
AI中文摘要：
动态图像图构建（DIGC）是FPGA加速视觉图神经网络（ViGs）中的主要性能瓶颈，它通过不规则、内存密集型的计算在每一层重建图连通性。现有的FPGA加速器优化了DIGC，但仍然无条件地执行它，使得重复的图重建成为延迟和能耗的持续来源。我们提出了SpecReuse算法，该算法计算中间特征的紧凑谱描述符，并在描述符漂移低于校准阈值时复用先前构建的图。我们进一步提出了SpecReuse加速器，这是一种FPGA架构，通过轻量级硬件实现谱描述符提取和复用控制，从而实现图复用，同时与现有的图构建加速器保持兼容。实验结果表明，端到端推理速度最高提升2.69倍，每次推理能耗降低约58%至65%，且FPGA资源开销可忽略不计，分类精度损失极小。
英文摘要：
Dynamic Image Graph Construction (DIGC) is the primary performance bottleneck in FPGA acceleration of Vision Graph Neural Networks (ViGs), reconstructing graph connectivity at every layer through irregular, memory-intensive computation. Existing FPGA accelerators optimize DIGC but still execute it unconditionally, making repeated graph reconstruction a persistent source of latency and energy consumption. We propose the SpecReuse algorithm, which computes compact spectral descriptors of intermediate features and reuses previously constructed graphs when descriptor drift remains below a calibrated threshold. We further present the SpecReuse accelerator, an FPGA architecture that realizes graph reuse through lightweight hardware for spectral descriptor extraction and reuse control while remaining compatible with existing graph-construction accelerators. Experimental results demonstrate up to a $2.69\times$ speedup in end-to-end inference and approximately 58--65\% lower energy per inference with negligible FPGA resource overhead and minimal loss in classification accuracy.
