发表机构
Lawrence Berkeley National Laboratory（劳伦斯伯克利国家实验室）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
针对超导量子比特通量预失真，提出误差有界的定点IIR滤波器设计方法，采用超采样率与分散前瞻流水线，在QubiC平台实现500MHz时钟下的实时校正。
AI 中文摘要
超导处理器中通量激活的双量子比特门需要校正线路失真，否则会产生残余失谐、条件相位误差和泄漏。先前基于低温冷冻镜的失真校准演示通常使用商业解决方案，这些方案指定了滤波器模型但未指定其FPGA实现。这些细节对于定制和开源系统至关重要，因为定点系数和数据路径格式决定了校正实现的准确性，而标准形式的IIR反馈回路在所需时钟频率下无法满足时序要求。我们根据阶跃响应误差容限推导出校正滤波器的系数格式，利用量化引起的极点和零点位移在每种失真的物理参数范围内的界限，以及累加器格式则根据输出端必须保持可分辨的最小输入变化来确定。同样的分析给出了量化保持滤波器稳定性的条件。我们在QubiC平台上以\SI{500}{MHz}的制造时钟频率实现了所得的FIR/IIR级联，采用具有分散前瞻流水线的超采样率结构，该结构在不改变目标传递函数的情况下消除了关键路径中的反馈递归。我们用于\SI{1}{GS/s}通量线的代表性级联，包括一个积分器、一个二阶节和一个20抽头FIR，消耗88个DSP切片并增加\SI{162}{ns}的延迟。我们通过校正特征偏置T型失真来确认硬件实现，这是迈向基于冷冻镜的完整校准的中间步骤。
英文摘要
Flux-activated two-qubit gates in superconducting processors require correction of line distortion, which otherwise produces residual detuning, conditional-phase error, and leakage. Prior demonstrations of cryoscope-based distortion calibration have generally used commercial solutions that specify the filter models but not their FPGA implementation. These details matter for custom and open-source systems, where the fixed-point coefficient and datapath formats set how accurately the correction is realized, and the IIR feedback loop in its standard form does not meet timing at the required clock rate. We derive the coefficient formats of the correction filters from a step response error tolerance, using bounds on the quantization-induced displacement of the poles and zeros over the physical parameter range of each distortion, and the accumulator format from the smallest input change that must remain resolvable at the output. The same analysis gives the conditions under which quantization preserves filter stability. We implement the resulting FIR/IIR cascade on the QubiC platform at a fabric clock rate of \SI{500}{MHz}, using a super-sample-rate structure with scattered look-ahead pipelining, which removes the feedback recursion from the critical path without changing the target transfer function. A representative cascade for our \SI{1}{GS/s} flux lines, comprising an integrator, a second-order section, and a 20-tap FIR, consumes 88 DSP slices and adds \SI{162}{ns} of latency. We confirm the hardware implementation by correcting characteristic bias-tee distortion, an intermediate step toward full cryoscope-based calibration.
Commentsv2: Fixed DoE acknowledgement
