发表机构
School of Electrical, Computing and Software Engineering, University of Arizona（亚利桑那大学电气、计算机与软件工程学院）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本研究利用[[8,3,3]]非CSS码和块级构造实现容错量子模拟，通过辛换位映射逻辑Trotter电路，分析了故障传播机制并评估多种缓解方法，展示了非CSS码块级容错的潜力。
AI 中文摘要
小型高码率非CSS稳定子码为编码量子计算提供了紧凑的平台，但混合泡利校验和有限的本地横向逻辑门使容错动力学复杂化。块级构造提供了一种替代方案，通过将整个逻辑块映射到物理电路，而不是分别编译受保护的逻辑门。我们以高码率[[8,3,3]]非CSS码和逻辑Trotter电路为测试平台研究了这种方法。我们构造了带标志的综合征提取电路，并建立了接近\(1.5\ imes10^{-3}\)的电路级存储器伪阈值。然后我们应用辛换位构造，该构造将逻辑Trotter电路映射到具有相同块模式的物理电路，适用于任何稳定子码。尽管这种映射在代数上保留了预期的酉算子，但编码Trotter电路在逻辑\(X\)和逻辑\(Z\)失效通道之间表现出不对称性。单故障分析确定了机制：共享奇偶校验辅助位上的故障可以通过反计算网络传播到不可检测的逻辑算子，从而降低受影响扇区的有效电路距离。我们评估了标志条件恢复、偏置噪声解码、CliNR资源验证、标志后选择和不对称门噪声模型。这些方法抑制了传播故障，但在所研究的现实配置中不能同时抑制两个逻辑扇区。移除已识别的恶性一阶位置的诊断性保护极限恢复了两个扇区的伪阈值行为，接近存储器性能。这些结果证明了块级逻辑构造在缺乏丰富本地横向门集的非CSS码上的潜力，以及保护容错距离所需的奇偶校验网络、模拟旋转和恢复的联合保护。
英文摘要
Small high-rate non-CSS stabilizer codes provide compact platforms for encoded quantum computation, but mixed-Pauli checks and limited native transversal logical gates complicate fault-tolerant dynamics. Block-level constructions offer an alternative by mapping an entire logical block to a physical circuit rather than compiling separately protected logical gates. We investigate this approach using the high-rate [[8,3,3]] non-CSS code and logical Trotter circuits as a testbed. We construct flagged syndrome-extraction circuits and establish a circuit-level memory pseudo-threshold near \(1.5\times10^{-3}\). We then apply our symplectic-transvection construction, which maps a logical Trotter circuit to a physical circuit with the same block pattern for any stabilizer code. Although this mapping preserves the intended unitary algebraically, encoded Trotter circuits exhibit asymmetry between logical-\(X\) and logical-\(Z\) failure channels. Single-fault analysis identifies the mechanism: a fault on the shared parity ancilla can propagate through the uncomputation network into an undetectable logical operator, reducing the effective circuit distance in the affected sector. We evaluate flag-conditioned recovery, biased-noise decoding, CliNR resource verification, flag postselection, and asymmetric gate-noise models. These methods suppress propagated faults but do not simultaneously suppress both logical sectors in the realistic configurations studied. A diagnostic protected limit removing the identified malignant first-order locations restores pseudo-threshold behavior in both sectors, approaching memory performance. These results demonstrate the potential of block-level logical constructions for non-CSS codes without rich native transversal gate sets and the joint protection of the parity network, analog rotation, and recovery required to preserve fault-tolerant distance.
Comments29 pages, 21 figures
