A7 CFET 与 A10 NSFET 技术的系统-技术协同评估：从单元寄生效应到芯片可靠性
System-Technology Co-Evaluation of A7 CFET and A10 NSFET Technologies from Cell Parasitics to Chip Reliability
- Technical University of Munich（慕尼黑工业大学）
- University of Modena and Reggio Emilia（摩德纳和雷焦艾米利亚大学）
- Applied Materials（应用材料公司）
机构由 AI 辅助整理，请以论文原文为准。
AI总结：
本文提出一种基于物理的热与老化感知STCO流程，对比A7 CFET与A10 NSFET，发现CFET在寄生RC下仍实现面积、功耗和温度大幅降低，并显著抑制BTI老化，提升芯片可靠性。
AI中文摘要：
互补场效应晶体管（CFET）通过垂直堆叠n型和p型全环绕栅极（GAA）器件，延续了纳米片场效应晶体管（NSFET）的缩放，从而缩小了标准单元面积。然而，性能提升不能仅从器件指标评估，因为CFET布局也引入了更大的单元级寄生电阻和电容（RC）。在这项工作中，我们提出了一种基于物理的热感知和老化感知的系统-技术协同评估（STCO）流程，用于评估A7 CFET和A10 NSFET技术节点中的寄生RC。我们的流程连接了校准的器件模型、优化的标准单元生成、自动化的GDS到TCAD转换（实现精确的3D寄生RC提取）、AI加速器的完整RTL到GDS实现、多物理场热分析以及基于物理的偏置温度不稳定性（BTI）老化评估。对两种技术使用相同的器件模型，我们可以在设计流程的不同层面隔离寄生RC和设计的影响。AI加速器设计的结果表明，相对于A10 NSFET基线，A7 CFET将芯片面积减少了24.7%，总导线长度减少了12%，面积效率TOPS/mm^2提高了74%。在等频率运行下，结果显示CFET电压缩放将功耗降低了68%，并将功率密度从148 W/cm^2降至55 W/cm^2，从而将芯片温度从125摄氏度降至仅62摄氏度。由此产生的应力温度降低抑制了10年BTI引起的退化达39%，所需的老化时序裕度减少了53%。
英文摘要：
Complementary FETs (CFETs) extend nanosheet FET (NSFET) scaling by vertically stacking n- and p-type gate-all-around (GAA) devices, thereby shrinking standard-cell area. The performance gain, however, cannot be assessed from device metrics alone, as CFET layouts also introduce larger cell-level parasitic resistance and capacitance (RC). In this work, we present a physics-based thermal- and aging-aware system-technology co-evaluation (STCO) flow to assess parasitic RCs in A7 CFET and A10 NSFET technology nodes. Our flow links calibrated device models, optimized standard-cell generation, automated GDS-to-TCAD conversion enabling accurate 3D parasitic RC extraction, full RTL-to-GDS implementation for an AI accelerator, multiphysics thermal analysis, and physics-based bias temperature instability (BTI) aging evaluation. Using the same device model for both technologies, we can isolate the impact of parasitic RCs and design at different levels of the design flow. The results of the AI accelerator design demonstrate that the A7 CFET reduces the chip area by 24.7% and the total wire length by 12%, improving the area efficiency TOPS/mm^2 by 74% relative to the baseline of the A10 NSFET. Under iso-frequency operation, results reveal that CFET voltage scaling reduces power by 68% and lowers power density from 148 W/cm^2 to 55 W/cm^2, which reduces the chip's temperature from 125 degrees C down to merely 62 degrees C. The resulting reduction in stress temperature suppresses 10-year BTI-induced degradation by 39%, reducing the required aging timing guardband by 53%.
