发表机构
School of Integrated Circuits, Peking University; School of Integrated Circuits, SJTU; Peking University Shenzhen Graduate School; School of Integrated Circuits, ECNU（北京大学集成电路学院; 上海交通大学集成电路学院; 北京大学深圳研究生院; 华东师范大学集成电路学院）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文首次提出通过翻转和背面工艺实现DRAM扩展，在4F2和3D-DRAM上验证了2F2 FVCT与翻转字线设计，显著降低寄生、提升速度与密度。
AI 中文摘要
我们首次提出了一种通过翻转和背面工艺实现DRAM扩展的新型堆叠技术，充分利用DRAM晶圆的背面，并在4F2和3D-DRAM上进行了研究。对于4F2 VCT，研究了具有自对准背对背堆叠1T1C位单元、多种位线（BL）和字线（WL）配置的2F2 Flip VCT，并成功开发了自对准堆叠垂直沟道、BL和WL形成、晶圆键合与翻转、衬底减薄以及低电阻钴（Co）存储节点（SN）等关键工艺模块，解决了Flip VCT工艺中潜在的热、对准和寄生问题。还建立了一个从器件到阵列（mat）和芯片级别的完整DRAM DTCO框架。与相同阵列尺寸的4F2 VCT DRAM相比，2F2 FVCT的寄生电容减少27.5%，读出裕度提高11%，电荷共享（CS）速度提高16.3%，面积减少50%。对于3D-DRAM，研究了一种全新的翻转字线阶梯设计及外围电路创新，证明其密度提升25%，开启速度加快15.1%，CS时间减少6.8%，证明了翻转技术在DRAM上的进一步可扩展性。
英文摘要
For the first time, we proposed a novel stacking technology for DRAM scaling by flipping and backside processes, making full use of DRAM wafer's backside and investigating it on both 4F2 and 3D-DRAM. For 4F2 VCT, 2F2 Flip VCT featuring self-aligned back-to-back stacked 1T1C bitcell, with various BL and WL configurations, were studied and key process modules such as self-aligned stacked vertical channel, BL and WL formations, wafer bonding and flipping, substrate thinning and low-R Co storage node (SN) were successfully developed, addressing the potential thermal, misalign and parasitic concerns in the Flip VCT process. A full DRAM DTCO framework was also established from device to mat and chip level. Compared to 4F2 VCT DRAM with the same mat size, 2F2 FVCT delivers 27.5% less parasitics, 11% better sense margin, 16.3% higher charge sharing (CS) speed and 50% less area. For 3D-DRAM, a brand-new flip WL staircase design with peripheral circuit innovations was studied and proved to have 25% density gain, 15.1% faster turn-on speed and 6.8% less CS time, proving further extendibility of flip technology on DRAM.
