发表机构
University of Cambridge（剑桥大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
WISER提出跨层设计空间探索框架，评估WISE全局控制囚禁离子架构的容错可行性，发现其可行空间狭窄，且布线可扩展性与逻辑吞吐量存在根本权衡，需大幅降低物理错误率和电路深度。
AI 中文摘要
囚禁离子量子计算机是可扩展容错量子计算的主要候选方案之一，但传统的量子电荷耦合器件（QCCD）架构在系统扩展时面临严重的布线和功耗限制。近期提出的WISE架构有望将布线复杂度降低数个数量级，但该架构从根本上改变了硬件-软件接口，使得此类受限架构能否可行地执行量子纠错（QEC）并最终支持容错工作负载变得不明确。我们提出了WISER，一个针对全局控制囚禁离子系统的跨层架构设计空间探索框架，旨在确定WISE能否支持早期容错量子计算（FTQC），以及需要哪些硬件/编译器/QEC选择。WISER结合了新颖的WISE专用编译、噪声建模和模拟，并将它们集成到一个统一框架中。WISER提供逻辑时钟速度和逻辑错误率的比较性下界估计，而非绝对硬件预测，使我们能够识别可行的操作区域，同时排除不可行的区域。据我们所知，这是首个针对WISE及超越QCCD的可扩展架构的系统性设计空间探索研究。使用WISER，我们识别出一个狭窄的可行设计空间，需要双离子阱、适度的控制多路复用、积极的再冷却和高码率双变量自行车码。即使在物理错误率改进约10倍的情况下，实现低于$10^{-8}$逻辑错误率的下界周期时间约为$100\,ms$，比局部控制慢3倍。这些结果揭示了布线可扩展性与逻辑吞吐量之间的根本权衡，表明实用的早期容错操作需要互补的超过10倍的物理错误率降低以及超过100倍的容错电路深度降低。
英文摘要
Trapped-ion Quantum Charge-Coupled Devices (QCCD) are a leading contender for quantum computing, but their scalability is constrained by control wiring and electronics. Wiring using Integrated Switching Electronics (WISE), a recently proposed QCCD architecture, reduces wiring through multiplexing and integrated switching hardware. However, this leaves an execution model with limited parallelism and limited flexibility in ion movement. Further, these devices need to be paired with a quantum error correction (QEC) code to enable fault-tolerant quantum computation (FTQC). Can WISE architectures efficiently support FTQC requirements? Which QEC choices, device and control parameters are practical? We present WISER, a cross-layer design-space exploration framework for trapped-ion systems with multiplexed control. WISER combines a WISE-specific SAT-based compiler, a physics-informed noise model and logical-memory simulation to estimate logical error rates, logical clock speeds and control power across hardware parameters and QEC families. Its compiler reduces routing time by $2.6$--$18.8\times$ relative to a greedy WISE-compatible baseline. Our analysis provides concrete design guidance. Two-ion traps with $16$-way multiplexing, $8\times$ lower than the original WISE proposal, give the fastest logical clock that meets our reliability and cold-stage power targets. With current hardware parameters, the distance-7 surface code is the only evaluated code to meet our early-FTQC screen, at $4.58\,$Hz and $2.04\,$W of DAC power per logical qubit. At this operating point, ion transport and recooling take $94$--$96\%$ of the WISE cycle, and even without them sample-and-hold electrode charging leaves millisecond-scale syndrome-extraction rounds.
CommentsVersion 2, 31 pages, 12 figures, 5 tables
