nBMS：一种用于eVTOL飞行器的神经形态电池管理系统，具有硅验证的尖峰荷电状态核心
nBMS, a Neuromorphic Battery Management System with a Silicon-Validated Spiking State-of-Charge Core for eVTOL Aircraft
- Istinye University（伊斯坦耶大学）
机构由 AI 辅助整理，请以论文原文为准。
AI总结：
针对eVTOL飞行器，提出一种基于事件驱动尖峰网络的神经形态电池管理系统nBMS，其SoC估计核心在零MAC运算下达到2.45% RMSE，并在FPGA上硅验证，实现低功耗高能效。
AI中文摘要：
电动垂直起降（eVTOL）飞行器的荷电状态（SoC）估计必须在严苛的能量和认证预算下于飞行器上运行，其工作周期与汽车文献中的任何情况都不同。在本研究中，设计了一个事件驱动的尖峰网络，作为nBMS神经形态电池管理架构的状态估计核心，用于逐时间步的SoC估计，并在一个公开的22节电池eVTOL数据集上进行了评估，同时以汽车数据集作为交叉验证。一个delta和群体编码器、一个二阶sigma-delta尖峰层以及一个速率累加器读出层共持有34,433个int16参数，且零密集乘加（MAC）运算。该估计器达到了2.45%的均方根误差（RMSE），而调优的长短期记忆（LSTM）基线为1.74%，这一差距被表征为巡航中的时间混合限制；作为交换，在传感器噪声下，其退化速度比自适应漏积分发放控制慢1.6倍，并且每步大约需要3,500次加法，而LSTM需要67,700次乘加运算。整个核心部署在低成本、汽车级认证的Artix-7现场可编程门阵列上，块RAM利用率达87%，在50 MHz下满足时序要求，并在硅片上复现了冻结的定点参考，在真实的491步飞行段上逐位精确。完全注释的实现后分析给出每次推理1.30微焦耳的能量消耗，在0.5 Hz任务节奏下平均功率为0.65微瓦。
英文摘要：
State-of-charge (SoC) estimation for electric vertical take-off and landing (eVTOL) aircraft must run on the vehicle under hard energy and certification budgets, on a duty cycle unlike anything in the automotive literature. In this study an event-driven spiking network, the state-estimation core of the nBMS neuromorphic battery management architecture, is designed for per-timestep SoC estimation and evaluated on a public 22-cell eVTOL dataset with an automotive cross-check. A delta and population encoder, a second-order sigma-delta spiking layer, and a rate-accumulator readout hold 34{,}433 int16 parameters with zero dense multiply-accumulate (MAC) operations. The estimator reaches 2.45\% root-mean-square error (RMSE) against 1.74\% for a tuned long short-term memory (LSTM) baseline, a gap characterized as a temporal-mixing limit in cruise; in exchange it degrades 1.6 times slower than an adaptive leaky integrate-and-fire control under sensor noise and needs roughly 3{,}500 additions per step where the LSTM needs 67{,}700 multiply-accumulates. The full core is deployed on a low-cost automotive-qualified Artix-7 field-programmable gate array at 87\% block-RAM utilization, meets timing at 50~MHz, and reproduces the frozen fixed-point reference bit-exactly over a real 491-step flight segment on silicon. Fully annotated post-implementation analysis gives 1.30~$μ$J per inference, an average of 0.65~$μ$W at the 0.5~Hz mission cadence.
