AI 中文总结
针对三维集成电路布图规划解空间大、层间延迟不均的问题，提出无分区式框架Great3D，统一优化互连与CPI，结合SDP全局嵌入与动态规划层分配，显著降低线长并提升性能。
AI 中文摘要
采用细间距混合键合的三维集成技术为缓解传统二维集成电路中的互连瓶颈提供了一条有前景的路径，然而，由于解空间扩大以及层间通信延迟不均匀，高效的三维布图规划仍然具有挑战性。现有方法要么将二维表示扩展到三维，导致组合复杂度高，要么采用先分区再规划的流程，过早固定模块到芯片层的分配，阻碍了布图规划、芯片层分配和垂直互连的联合优化。在本工作中，我们提出了Great3D，一个无分区式三维布图规划框架，直接优化原生三维布图。Great3D构建了一个统一的目标函数，将互连成本与基于每周期指令数（CPI）的延迟项耦合，以捕捉面对面（F2F）键合对系统级的影响。在算法上，它结合了基于半定规划（SDP）的三维全局嵌入和用于芯片层分配的动态规划细化，随后进行考虑实际设计约束的二维连续细化。在GSRC和ATPlace基准测试集上的实验表明，与最先进的三维布图规划器相比，Great3D在线长和CPI质量上 consistently 取得优异结果。在GSRC上，与竞争的三维原生布图规划器相比，总线长最多减少约70%（平均减少2.40至2.74倍），其动态规划芯片层分配阶段进一步将CPI提高9.5%至17.8%，同时在多达数百个模块的实例上保持有竞争力的运行时间。
英文摘要
3D integration with fine-pitch hybrid bonding offers a promising path to alleviate interconnect bottlenecks in conventional two-dimensional (2D) ICs, yet efficient 3D floorplanning remains challenging due to the enlarged solution space and non-uniform inter-die communication latency. Existing methods either extend 2D representations into 3D, leading to combinatorial complexity, or adopt partitioning-first pipelines that fix block-to-die assignments early and hinder joint optimization of floorplan, die assignment, and vertical connectivity. In this work, we present \textsc{Great3D}, a partitioning-free 3D floorplanning framework that directly optimizes a native 3D floorplan. \textsc{Great3D} formulates a unified objective that couples interconnect cost with a cycles-per-instruction (CPI)-derived latency term to capture the system-level impact of face-to-face (F2F) bonding. Algorithmically, it combines an SDP-based 3D global embedding with a dynamic-programming refinement for die assignment, followed by 2D continuous refinement with practical design constraints. \textcolor{blue}{Experiments on the GSRC and ATPlace benchmark suites show that \textsc{Great3D} consistently achieves strong wirelength and CPI quality against state-of-the-art 3D floorplanners. On GSRC, it reduces total wirelength by up to about $70\%$ (and by $2.40$--$2.74\times$ on average) over competing 3D-native floorplanners, and its dynamic-programming die-assignment stage further improves CPI by $9.5$--$17.8\%$, while maintaining competitive runtime on instances of up to a few hundred blocks.}
Comments13 pages, 10 figures
