发表机构
Universitat Politècnica de Catalunya - BarcelonaTech (UPC)（加泰罗尼亚理工大学-巴塞罗那理工（UPC））
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
针对忆阻SNN中传统电流读出开销大的问题，提出基于电压-时间转换的全模拟读出架构，避免电流求和电路，经130nm CMOS后布局仿真及64x10 SNN数字分类验证，提升了面积与能效。
AI 中文摘要
人工神经网络依赖于向量-矩阵乘法（VMM），在冯·诺依曼架构中，其实现受限于存储与处理单元之间高成本的数据移动。脉冲神经网络（SNN）通过使用忆阻交叉阵列执行存内模拟VMM来缓解这一瓶颈。然而，传统的电流模式读出电路会带来显著的面积和功耗开销。本文提出一种基于电压-时间转换的全模拟读出架构，用于VMM输出。通过感知列电压，所提方法避免了电流模式求和与缩放电路，从而提高了面积和能量效率。基于130纳米CMOS工艺实现的10x1 SNN的后布局仿真验证了所提架构，同时，将其应用于一个训练好的64x10 SNN进行数字分类，进一步证明了其在SNN推理中的可行性。
英文摘要
Artificial neural networks rely on vector-matrix multiplications (VMMs), whose implementation in von Neumann architectures is dominated by costly data movement between memory and processing units. Spiking neural networks (SNNs) mitigate this bottleneck by performing in-memory, analog VMMs using memristive crossbar arrays. However, conventional current-mode readout circuits incur significant area and power overhead. This work proposes a fully analog readout architecture based on voltage-to-time conversion of the VMM output. By sensing the column voltage, the proposed approach avoids current-mode summing and scaling circuitry, improving area and energy efficiency. Post-layout simulations of a 10x1 SNN implemented in a 130 nm CMOS technology validate the proposed architecture, while application to a trained 64x10 SNN for digit classification further demonstrates its feasibility for SNN inference.
CommentsAccepted at 2026 IEEE 33rd International Conference on Electronics, Circuits and Systems (ICECS)
