发表机构
Rensselaer Polytechnic Institute; IBM T.J. Watson Research Center（伦斯勒理工学院; IBM托马斯·J·沃森研究中心）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
REACH提出一种控制器微架构，利用内码纠错和外码擦除修复，差分奇偶校验限制写入流量，在保持性能的同时显著降低面积和功耗。
AI 中文摘要
高带宽存储器（HBM）的成本促使需要更强的控制器保护，以支持更广泛的设备错误率。长跨度纠错码在相当的码率下提供更强的保护，但直接实现会将小访问与跨度级状态耦合，并需要在HBM带宽下进行昂贵的解码。以读为主的LLM解码提供了一个有利的环境：顺序读取支持跨度聚合，而稀疏写入限制了奇偶校验更新流量。本文提出了REACH，一种控制器微架构，它使用成熟的内码来纠正常见错误并识别未解决的块，保留长外码用于已知擦除修复。差分奇偶校验限制了写入流量，协同设计的端点保持了32字节的事务，而无需额外的数据突发。Ramulator2在最高错误压力下维持了1.88 TB/s的应用流量，而单独的全接口尺寸调整支持2.69 TB/s的应用目标，使用ASAP7综合的内核。在此分析目标下，REACH的名义组合比评估的平均工作直接长跨度设计少使用55.8%的控制器面积和57.7%的建模功耗，显示了将长跨度恢复保留给异常请求的好处。
英文摘要
High-Bandwidth Memory (HBM) cost motivates stronger controller protection that can support a wider range of device error rates. Long-span error-correcting codes provide stronger protection at a comparable code rate, but a direct implementation couples small accesses to span-wide state and requires costly decoding at HBM bandwidth. Read-dominated LLM decode offers a favorable setting: sequential reads support span aggregation, while sparse writes limit parity-update traffic. This paper presents REACH, a controller microarchitecture that uses established inner codes to correct common errors and identify unresolved chunks, reserving a long outer code for known-erasure repair. Differential parity bounds write traffic, and a co-designed endpoint preserves 32\,B transactions without an extra data burst. Ramulator2 sustains 1.88\,TB/s of application traffic at the highest error stress, while separate full-interface sizing supports a 2.69\,TB/s application target using ASAP7-synthesized kernels. At this analytical target, REACH's nominal composition uses 55.8\% less controller area and 57.7\% less modeled power than the evaluated mean-work direct-long design, showing the benefit of reserving long-span recovery for exceptional requests.
