多QPU系统上量子电路的保真度感知调度
Fidelity-Aware Scheduling of Quantum Circuits on Multi-QPU Systems
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中文总结 AI 辅助
针对多QPU系统，提出基于图神经网络的保真度感知调度框架，编译前估计各电路在各QPU上的保真度，以权衡执行保真度与并行性，近似最优分配并节省计算资源。
中文摘要 AI 辅助
高性能计算-量子计算（HPCQC）平台暴露了多个量子处理单元（QPU），这些单元在规模、拓扑、原生门和噪声特性上可能有所不同。对于当前的噪声设备，错误沿编译后的电路迅速累积，最小化这些错误，即最大化电路执行的保真度，对于获得可靠结果至关重要。保真度取决于对特定目标设备的编译：相同的高级电路可能产生不同的可执行文件，因此在不同QPU上产生不同的预期保真度。我们提出了一种基于图神经网络（GNN）的低开销保真度感知调度框架，用于多QPU系统，该网络在编译前估计每个电路在每个可用QPU上的预期保真度。然后，一个可调调度器利用这些估计来控制执行保真度与并行性之间的权衡。结果表明，该框架能够近似于穷举的基于保真度的分配，与在每个设备上编译每个电路的暴力方法相比，节省了计算资源。
英文摘要
High Performance Computing-Quantum Computing (HPCQC) platforms expose multiple Quantum Processing Units (QPUs) that may differ in size, topology, native gates, and noise characteristics. For current noisy devices, errors compound along the compiled circuits quickly, and minimizing them, that is, maximizing the circuits' execution fidelity, is essential for reliable results. Fidelity depends on the compilation to a specific target device: the same high-level circuit may produce different executables and, therefore, different expected fidelities across QPUs. We present a low-overhead fidelity-aware scheduling framework for multi-QPU systems based on a Graph Neural Network (GNN) that estimates, before compilation, the expected fidelity of each circuit on each available QPU. Then, a tunable scheduler uses these estimates to control the trade-off between execution fidelity and parallelism. Results show that this framework allows for approximating an exhaustive fidelity-based assignment, saving computational resources compared to a brute-force approach that compiles each circuit on every device.
