发表机构
TU Darmstadt; TU Ilmenau（达姆施塔特工业大学; 伊尔默瑙工业大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
提出DiffLUT-Net，一种FPGA原生网络，通过可微训练联合学习六输入LUT的真值表和输入连接，训练后离散化并导出为Verilog，在五个基准上实现良好的精度-资源权衡。
AI 中文摘要
现场可编程门阵列（FPGA）能够实现高效的神经网络推理，但大多数部署流程要么加速乘累加操作，要么将预训练的量化模型转换为查找表（LUT）。我们提出了DiffLUT-Net，一种由六输入LUT连接而成的FPGA原生网络，该网络从头开始训练。我们通过可微的LUT函数松弛和硬件源选择，联合学习LUT的64个真值表条目以及其六个输入端口各自的源。训练后，真值表和连接被离散化，未使用的逻辑可以被剪枝，网络直接导出为可综合的Verilog。在五个基准测试中，DiffLUT-Net取得了良好的精度-资源权衡。这些结果证明了联合学习LUT函数和稀疏连接对于紧凑型FPGA原生推理的有效性。代码可在以下网址获取：此https URL。
英文摘要
Field-programmable gate arrays (FPGAs) enable efficient neural-network inference, but most deployment flows either accelerate multiply-accumulate operations or convert pretrained quantized models into lookup tables (LUTs). We present DiffLUT-Net, an FPGA-native network connected by six-input LUTs that are trained from scratch. We jointly learn the 64 truth-table entries of a LUT and the source to each of its six input ports using a differentiable LUT function relaxation and hardware source selection. After training, the truth tables and connections are discretized, unused logic can be pruned, and the network is exported directly as synthesizable Verilog. Across five benchmarks, DiffLUT-Net achieves favorable accuracy-resource trade-offs. These results demonstrate the effectiveness of jointly learning LUT functions and sparse connectivity for compact FPGA-native inference. The code is available at https://github.com/TUDa-HWAI/DiffLUT-Network.
