缩放型P型纳米片的晶圆级1/f噪声表征及其与平面HKMG晶体管的比较
Wafer-Level 1/f Noise Characterization of Scaled P-Type Nanosheets and Comparison with Planar HKMG Transistors
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中文总结 AI 辅助
本文通过晶圆级1/f噪声统计，比较了GAA p型纳米片与平面HKMG晶体管的有效陷阱密度，发现两者相当，表明架构转变不增加噪声，可靠性由栅极堆叠质量主导。
中文摘要 AI 辅助
我们展示了一项针对缩放型环栅（GAA）p型纳米片晶体管的全面晶圆级1/f噪声研究，并将其与大面积平面高k金属栅（HKMG）器件进行基准比较，以评估器件架构对可靠性的影响。通过对188个纳米片的噪声数据进行统计分析，我们提取了介电层中的有效陷阱密度，并将其与具有相同栅极堆叠、可比处理热预算且未经过特定可靠性退火的平面晶体管进行了比较。从1/f噪声中提取的有效陷阱密度在平面和纳米片架构中相当。这表明过渡到GAA纳米片并不会增加噪声，噪声仍由栅极堆叠质量决定。
英文摘要
We present a comprehensive wafer-level 1/f noise study of scaled Gate-All-Around (GAA) p-type nanosheet transistors and benchmark them against large-area planar High- \k{appa} Metal Gate (HKMG) devices to assess the impact of device architecture on reliability. By statistically analyzing noise data from 188 nanosheets, we extract the effective trap density in the dielectric and compare it to that of planar transistors with identical gate stack, comparable processing thermal budgets, and no specific reliability anneals. The effective trap density extracted from 1/f noise is comparable in planar and nanosheet architectures. This indicates that transitioning to GAA nanosheets does not increase noise, which remains governed by gate stack quality.
发表机构
- imec
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