利用基于CMP的平坦化技术制备高质量Nb/Al-AlO$_x$/Nb交叉型约瑟夫森隧道结及其表征
Fabrication And Characterization Of High-Quality Nb/Al-AlO$_x$/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
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中文总结 AI 辅助
本文采用CMP平坦化技术制备Nb/Al-AlOx/Nb交叉型约瑟夫森隧道结，消除寄生电容并提高良率至90%以上，通过IV特性和夫琅禾费图样表征结质量。
中文摘要 AI 辅助
约瑟夫森隧道结（JJs）是当今最先进的超导电子元件（如量子比特和超导量子干涉器件（SQUIDs））的基本构建单元。鉴于这些器件在晶圆尺度上持续存在的可扩展性需求，尽可能精确地控制制备工艺以确保均匀的质量和可重复性至关重要。目前，窗口型JJs常用于直流SQUIDs的生产，虽然它们可靠且可重复，但存在由光刻引起的对准误差和不可避免的寄生电容，从而限制了直流SQUIDs的能量灵敏度。这些问题可以通过制备具有交叉型几何结构的JJs来规避，交叉型结构允许更小的结面积并消除寄生电容。在此，我们讨论了基于Nb/Al-AlOx/Nb的交叉型JJs的制备，其中三层膜嵌入溅射沉积的SiO$_2$中，以实现结构的平坦化并确保底电极侧壁的可靠绝缘。我们采用化学机械抛光（CMP）来去除多余的SiO$_2$，而不是采用耗时且可能在微结构边缘留下不希望的翼状残留物从而影响后续层的剥离工艺。这不仅速度更快，而且能产生光滑均匀的表面，从而有效提高了我们JJ制备工艺的可靠性，在晶圆尺度上实现了超过90%的高良率。此外，我们讨论了制备细节对分布在晶圆上、面积小至1$\\,\mathrm{\mu m} \times 1\\,\mathrm{\mu m}$的不同结面积的JJs质量和电学性能的影响，并从其IV特性曲线和夫琅禾费衍射图样中提取了结特有的质量参数。
英文摘要
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO$_2$ to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO$_2$. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over $90\,\%$ on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to $1\,\mathrm{μm} \times 1\,\mathrm{μm}$ distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
发表机构
- Heidelberg University（海德堡大学）
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