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arXiv 2609.08075cs.PL

映射动态、层次化量子电路

Mapping Dynamic, Hierarchical Quantum Circuits

Marouane Benbetka, Merwan Bekkar, Bokyeong Yoon, Riyadh Baghdadi, Martin Kong

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中文总结 AI 辅助

本文提出一种新的量子比特映射方法,通过静态建模子电路、量子比特协调、循环入口重映射和增强成本函数,处理层次化动态电路,在单片和小芯片QPU上显著降低SWAP数、深度、延迟和错误率。

中文摘要 AI 辅助

量子比特映射是量子编译中的一个关键环节。尽管已有多种进展,但动态电路(即表现出数据依赖控制流、通常由量子比特测量导致的电路)尚未得到绝大多数现有量子比特映射器的支持。需要克服的关键限制在于对电路的扁平化、一维表示的依赖。此外,当前的量子比特映射器缺乏能够捕捉电路层次化特性的编译器抽象,这阻碍了量子比特映射过程。在本文中,我们引入了一种新的量子比特映射方法及分析,以处理层次化动态电路。我们的创新体现在四个关键方面:(静态地)对不相交控制流路径中的子电路进行建模,引入一种新颖的量子比特协调(Qubit Reconciliation)过程以维持子电路与控制流边界之间的一致性,一个循环入口重映射过程,以及一个针对SWAP数量、电路深度、电路延迟和错误率进行增强的精细化成本函数。我们在127量子比特和156量子比特的两个单片量子处理单元(QPU)以及基于六边形小芯片的QPU上,对多种动态电路展示了我们方法的效率。在单片QPU上,我们的量子比特映射器将SWAP数量最多改善52%,深度最多改善18%,延迟最多改善18.6%,错误率最多改善40%。在小芯片架构上,我们实现了SWAP数量最多36%、深度最多8.7%、延迟最多15%以及错误率最多15%的改善。

英文摘要

Qubit mapping is a critical pass in quantum compilation. Despite various advances, dynamic circuits, those exhibiting data dependent control-flow, often resulting from qubit measurements, are not yet supported by the vast majority of available qubit mappers. The crucial limitation to overcome is the dependence on flat, one-dimensional representations of circuits. Further, qubit mappers currently lack compiler abstractions that capture the hierarchical nature of circuits, hindering the qubit mapping process. In this paper, 1 we introduce a new qubit mapping method and analyses to tackle hierarchical dynamic circuits. Our novelty resides in four key aspects: modeling (statically) sub-circuits in disjoint control-flow paths, introducing a novel Qubit Reconciliation pass to maintain consistency between sub-circuit and control-flow boundaries, a loop-entry remapping pass, and a refined cost function enhanced for SWAP count, circuit depth, circuit latency and error. We demonstrate the efficiency of our approach on a wide range of dynamic circuits on two monolithic Quantum Processing Units of 127 and 156 qubits, and on chiplet hexagon-based QPUs. On monolithic QPUs, our qubit mapper improves the SWAP count by up to 52%, depth by up to 18%, latency by up to 18.6%, and error by up to 40%. On chiplet architectures, we achieve improvements of up to 36% on SWAP count, 8.7% on depth, 15% on latency, and 15% of error.

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