发表机构
Fudan University（复旦大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
提出可微划分框架，通过梯度优化三维IC布局感知层分配，引入双最大线长模型和端子感知惩罚，在OpenROAD基准上平均降低D2D HPWL 2.0%和12.1%。
AI 中文摘要
近年来，三维集成电路物理设计的研究迅速扩展。基于混合键合的三维集成电路在互连缩放和系统集成方面提供了显著优势，然而层分配仍然具有挑战性，因为它共同决定了三维线长和混合键合端子分配。本文提出了一种可微划分框架，通过基于梯度的优化直接优化三维集成电路的布局感知层分配。离散层分配被松弛为连续概率，并引入了一种双最大三维线长模型来捕获每层半周长线长。此外，一种端子感知的切割数惩罚选择性地抑制混合键合端子拥挤区域中的跨芯片网络，而局部平衡约束则强制跨层的网格单元密度均衡。在OpenROAD基准上的实验结果表明，与两种最小割基线相比，我们的方法平均将D2D半周长线长降低了2.0%，与最先进的三维布局器相比降低了12.1%。我们开源了我们的划分代码及三维布局流程，以支持可复现性。
英文摘要
Research on 3D-ICs physical design has expanded rapidly in recent years. Hybrid bonding-enabled 3D integrated circuits (3D-ICs) offer substantial benefits in interconnect scaling and system integration, yet tier assignment remains challenging because it jointly determines 3D wirelength and hybrid bonding terminal (HBT) assignment. This paper presents a differentiable partitioning framework that directly optimizes placement-aware tier assignment for 3D-ICs through gradient-based optimization. Discrete tier assignment is relaxed to continuous probabilities, and a Dual-Max 3D wirelength model is introduced to capture per-tier half-perimeter wirelength (HPWL). In addition, a terminal-aware cutsize penalty selectively suppresses cross-die nets in HBT-congested regions, and a local balance constraint enforces grid-cell density equilibrium across tiers. Experimental results on OpenROAD benchmarks show that our method reduces D2D HPWL by 2.0% on average over two min-cut baselines and by 12.1% over the state-of-the-art 3D placer. We open-source our partition code with 3D placement flow to support reproducibility.
