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TETRIS-Q:基于平铺的交错超导量子比特瞬态故障有效抑制方法

TETRIS-Q: Tiling-based Effective Transient-fault Reduction on Interleaved Superconducting Qubits

Marzio Vallero, Gioele Casagranda, Flavio Vella, Paolo Rech

arXiv 2609.05226首次发表:更新:

发表机构

University of Trento; Trento Institute for Fundamental Physics and Applications, National Institute for Nuclear Physics(特伦托大学; 特伦托基础物理与应用研究所,意大利国家核物理研究所)

机构由 AI 辅助整理,请以论文原文为准。

AI 中文总结

针对辐射引发的超导量子比特相关缺陷问题,提出TETRIS-Q方法结合声子势垒与QEC交错,经5100万次模拟实现逻辑错误大幅降低,同时降低相关成本。

AI 中文摘要

当前量子计算研究的核心挑战是有效抑制外部辐射与超导量子器件相互作用引发的误差机制。尽管近年量子纠错(QEC)技术已取得快速进展,但辐射引发的故障仍未得到完全解决,这类事件会导致同一衬底上的量子比特出现同时相关缺陷,最终损害QEC码的有效性。本文提出通过平面网格平铺算法TETRIS-Q,选择性结合衬底级声子势垒与QEC交错技术,实现对辐射事件的高效且有效抑制。该跨层方案不会增加QEC码执行或解码时间的额外成本。我们对多种势垒和QEC交错配置下的辐射引发瞬态故障进行建模与模拟,通过超过5100万次量子电路模拟,结果显示:采用可渗透势垒时,峰值逻辑错误降低幅度超过99.8%,可观测瞬态持续时间降低80%;更稀疏的平铺可达到与单量子比特平铺相当的性能,使势垒追踪成本降低87%以上;通过利用独立QEC码交错,不使用可渗透势垒时平均逻辑错误率可降低一个数量级,联合使用势垒时可降低三个数量级。

英文摘要

The struggle of the hour in quantum computing research is achieving effective suppression of the error mechanisms induced by the interaction of external radiation with superconducting quantum devices. Despite the rapid advancements in quantum error correction (QEC) of recent years, radiation-induced faults are yet to be fully addressed. These events are known to be the cause of simultaneous correlated defects in qubits that lie onto a single substrate, ultimately jeopardising QEC code effectiveness. In this paper, we propose to selectively combine substrate-level phonon barriers and QEC interleaving via a planar-mesh tiling algorithm, TETRIS-Q, reaching efficient and effective suppression of radiation events. Our cross-layer solution comes at no extra cost in terms of QEC code execution or decoding time. We model and simulate radiation-induced transient faults over a plethora of barrier and QEC interleaving configurations. Through more than 51 million quantum circuit simulations, we show peak logical error reductions of more than $99.8 \%$, together with an $80\%$ reduction of the observable transient duration with permeable barriers. We find that sparser tiling can reach comparable performance to single qubit tiling, prompting cost reductions of upwards of $87 \%$ in barrier tracing. By leveraging independent QEC code interleaving, we measure up to one order of magnitude average logical error rate reductions without the use of permeable barriers, and up to three orders of magnitude with the joint usage of barriers.

Comments10 pages, 8 figures

论文原文

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