发表机构
The Chinese University of Hong Kong（香港中文大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
LevelSyn是一种基于层级异步GNN的物理感知逻辑综合框架，通过层级对齐子图划分策略适配工业级设计，在EPFL基准上较SOTA方法实现功耗降6.89%、延迟升27.48%，DRC违规减99.59%，可加速集成电路设计收敛。
AI 中文摘要
随着集成电路工艺缩小至纳米级，传统逻辑综合与物理设计的脱节导致PPA（功耗、性能和面积）显著下降，且设计收敛周期延长。传统逻辑综合依赖非物理的线负载模型（WLM），而近期基于谱的布局预测器常忽略网表固有的层级逻辑深度与信号流，导致空间估计保真度低。为弥合该差距，本文提出LevelSyn，一种新颖的物理感知逻辑综合框架，将层级表征学习与线长驱动的优化引擎相结合。LevelSyn的核心是利用层级异步图神经网络（GNN），通过捕捉与非门图（AIG）的结构与方向语义来预测高保真度的门坐标。为处理工业级设计，引入层级对齐的子图划分策略，在保留局部逻辑依赖的同时消除内存瓶颈。这些空间见解被无缝集成到伯克利ABC框架内新开发的物理感知综合引擎中。在EPFL基准套件上的实验结果表明，LevelSyn显著优于当前最先进（SOTA）方法，实现平均功耗降低6.89%、时序延迟改善27.48%；此外，布局后布线验证显示设计规则检查（DRC）违规减少99.59%，凸显其在加速设计收敛方面的有效性。
英文摘要
As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Performance, and Area) degradation and prolonged design closure cycles. Traditional logic synthesis relies on non-physical Wire Load Models (WLMs), while recent spectral-based placement predictors often neglect the inherent hierarchical logic depth and signal flow of netlists, which leads to low-fidelity spatial estimations. To bridge this gap, we propose LevelSyn, a novel physical-aware logic synthesis framework that integrates hierarchical representation learning with a wirelength-driven optimization engine. At its core, LevelSyn leverages a level-asynchronous Graph Neural Network (GNN) to predict high-fidelity gate coordinates by capturing the structural and directional semantics of And-Inverter Graphs (AIGs). To handle industrial-scale designs, a level-aligned subgraph partitioning strategy is introduced to eliminate memory bottlenecks while preserving local logical dependencies. These spatial insights are seamlessly integrated into a newly developed physical-informed synthesis engine within the Berkeley ABC framework. Experimental results on the EPFL benchmark suite demonstrate that LevelSyn significantly outperforms state-of-the-art (SOTA) methods, achieving an average power reduction of 6.89\% and a timing delay improvement of 27.48\%. Furthermore, post-place-and-route validation shows a 99.59\% reduction in design rule check (DRC) violations, highlighting its effectiveness in accelerating design convergence.
