利用Parity Twine优化原子传输、门数量与电路深度
Optimizing Atom Transport, Gate-Count and Depth with Parity Twine
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中文总结 AI 辅助
该研究针对中性原子量子处理器，通过适配不同原生纠缠门开发PTN构造，优化量子电路的门数量、原子传输与深度，30量子比特QFT的电路保真度较竞争策略提升三个数量级，且可扩展至其他量子算法。
中文摘要 AI 辅助
我们提出了中性原子量子处理器的Parity架构的高效实现方案。我们将Parity Twine网络（PTNs）适配到不同的原子布局、原生纠缠门及原子穿梭能力，为在通用基下编码任意相互作用图的量子电路提供了门数量、电路深度与原子传输的硬件感知优化的通用框架。具体而言，我们基于CZ、CZSWAP和iSWAP这三种不同的原生纠缠门实现方式开发了PTN构造，可适配静态和移动中性原子平台上的不同硬件能力。以量子傅里叶变换（QFT）为代表性示例，我们证明了两量子比特门数量、原子传输和电路深度的大幅减少。对于30量子比特QFT，这些资源节省转化为比竞争编译策略高三个数量级的估计电路保真度。我们还将该构造扩展到近期提出的乐观QFT，并讨论了PTNs在中性原子平台上对其他量子算法的更广泛适用性。
英文摘要
We present an efficient implementation of the Parity Architecture for neutral-atom quantum processors. We adapt Parity Twine Networks (PTNs) to different atom layouts, native entangling gates, and atom-shuttling capabilities. This provides a general framework for hardware-aware optimization of gate count, circuit depth, and atom transport for quantum circuits encoding arbitrary interaction graphs in a common basis. Specifically, we develop PTN constructions based on different native entangling-gate realizations, namely CZ, CZSWAP, and iSWAP, providing flexibility to accommodate different hardware capabilities on both static and mobile neutral-atom platforms. Using the quantum Fourier transform (QFT) as a representative example, we demonstrate substantial reductions in two-qubit gate count, atom transport, and circuit depth. These resource savings translate into an estimated circuit fidelity three orders of magnitude higher than competing compilation strategies for a 30-qubit QFT. We further extend the construction to the recently introduced optimistic QFT and discuss the broader applicability of PTNs to other quantum algorithms on neutral-atom platforms.
发表机构
- Parity Quantum Computing Germany GmbH（Parity量子计算德国有限公司）
- Parity Quantum Computing GmbH（Parity量子计算有限公司）
- Institute for Theoretical Physics, University of Innsbruck（因斯布鲁克大学理论物理研究所）
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