发表机构
Quantinuum（Quantinuum）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本研究基于[[20,2,6]] C₄-Helix码，在98量子比特离子阱处理器Quantinuum Helix上实验验证了一款容错架构，实现了低误差量子纠错、逻辑克利福德操作及跨码型接口，性能优于未编码基线。
AI 中文摘要
量子纠错（QEC）正开始实现性能优于未编码物理对应物的逻辑操作，但实用的容错计算所需的不仅是低误差量子存储器。有效架构必须协调高效的逻辑编码、低开销的逻辑操作，以及通用计算所需的非克利福德资源的访问。在此，我们引入并实验验证了一种基于[[20,2,6]] C₄-Helix码的架构，该架构专为早期容错机制设计。使用Quantinuum Helios（一款98量子比特的离子阱量子处理器），我们实验演示了该架构的主要组件：我们执行重复量子纠错，每个逻辑量子比特每个QEC周期的误差为4.6⁺⁶.²₋₂.₆×10⁻⁵。我们在主动纠错下对单个码块的两个逻辑量子比特上的完整克利福德组进行基准测试，每两量子比特逻辑克利福德的误差为2.8⁺¹.⁰₋¹.⁶×10⁻⁴。我们进一步演示了C₄-Helix与距离5表面码之间的容错链映射接口，制备了异质三逻辑量子比特GHZ态，其保真度下界为99.925⁺⁰.⁰⁶⁸₋₀.²⁴⁵%。在每种情况下，编码后的实现均优于其对应的未编码物理基线，且不依赖后选择。电路级模拟表明，物理保真度的提升可使同一架构进入早期容错计算目标的10⁻⁶-10⁻⁸逻辑误差 regime。这些结果共同确立了C₄-Helix为硬件验证的容错架构，而非单纯的量子存储器。
英文摘要
Quantum error correction (QEC) is beginning to enable logical operations that outperform their unencoded physical counterparts, but useful fault-tolerant computation will require more than low-error quantum memory. An effective architecture must orchestrate efficient logical encoding, low-overhead logical operations, and access to the non-Clifford resources required for universal computation. Here, we introduce and experimentally validate such an architecture based on the $[[20,2,6]]$ $C_4$-Helix code, designed for the early fault-tolerant regime. Using Quantinuum Helios, a 98-qubit trapped-ion quantum processor, we experimentally demonstrate the principal components of this architecture: we perform repeated quantum error correction with an error of $4.6^{+6.2}_{-2.6}\times10^{-5}$ per logical qubit per QEC cycle. We benchmark the complete Clifford group on the two logical qubits of a single codeblock under active error correction, obtaining an error of $2.8^{+1.0}_{-1.6}\times 10^{-4}$ per two-qubit logical Clifford. We further demonstrate a fault-tolerant chain-map interface between $C_4$-Helix and a distance-5 surface code, preparing a heterogeneous three-logical-qubit GHZ state with a fidelity lower bound of $99.925^{+0.068}_{-0.245}\%$. In each case, the encoded implementation outperforms its corresponding unencoded physical baseline without relying on postselection. Circuit-level simulations indicate that improvements in physical fidelity bring the same architecture into the $10^{-6}$-$10^{-8}$ logical-error regime targeted for early fault-tolerant computation. Together, these results establish $C_4$-Helix as a hardware-validated fault-tolerant architecture rather than a bare quantum memory.
Comments18 pages, 14 figures
