面向TCAD闭环设计空间探索的原生网格物理信息图代理模型
Mesh-Native Physics-Informed Graph Surrogates for TCAD-in-the-Loop Design Space Exploration
浏览论文内容
中文总结 AI 辅助
本文提出原生网格物理信息图注意力网络代理模型，直接处理TCAD网格，结合物理损失训练，通过主动学习筛选设计，在多鳍FinFET上精度优异，吞吐量远高于全模拟器，可实现跨器件规模帕累托前沿探索。
中文摘要 AI 辅助
漂移-扩散输运的高保真TCAD（技术计算机辅助设计）模拟仍是新兴FinFET器件设计的核心手段，但计算成本高昂，尤其对于三维结构，运行时间随网格复杂度急剧增加，这极大限制了多目标设计空间探索。现有机器学习代理模型将固定设计参数集映射到少数标量器件指标，忽略了底层物理规律，且在器件几何结构和系列间缺乏可迁移性。本文提出一种物理信息图注意力网络（GAT）代理模型，其直接作用于四面体TCAD网格，在每个网格节点处预测漂移-扩散系统的基本未知量：静电势以及电子和空穴的准费米能级。训练过程结合数据损失与有限体积电流连续性残差，将载流子输运物理规律嵌入目标函数。由于以图形式处理网格，该代理模型具备尺寸泛化能力：在少鳍网格上训练的模型可直接应用于大得多的阵列，推理阶段仅受GPU内存限制。深度集成产生的节点级不确定性驱动主动学习循环，该循环可在数秒内筛选大量候选池，仅将信息最丰富的设计转发至全模拟。在多鳍三栅FinFET上与Sentaurus Device基准测试对比，该代理模型再现三个漂移-扩散场时，每个场的RMSE（均方根误差）低于1伏，且每设计的吞吐量比全模拟器高几个数量级。该优势随器件尺寸增大而提升：对于直接模拟速度极慢的大型多鳍阵列，推理仍可在每器件不到一秒内完成，实现了直接TCAD扫描无法完成的跨器件规模帕累托前沿探索。
英文摘要
High-fidelity TCAD simulation of drift-diffusion transport remains the workhorse of emerging FinFET device design, but it is computationally expensive, especially for 3D structures where runtime escalates steeply with mesh complexity. This sharply limits multi-objective design space exploration. Existing machine-learning surrogates map a fixed set of design parameters to a few scalar device metrics, discarding the underlying physics and losing transferability across device geometries and families. A physics-informed graph attention network (GAT) surrogate is proposed. It operates directly on the tetrahedral TCAD mesh and predicts, at every mesh node, the electrostatic potential together with the electron and hole quasi-Fermi levels, the fundamental unknowns of the drift-diffusion system. Training combines a data loss with finite-volume current-continuity residuals, embedding carrier-transport physics into the objective. Operating on the mesh as a graph, the surrogate inherits size generalization: a model trained on few-fin meshes applies unchanged to substantially larger arrays, bounded at inference only by GPU memory. Per-node uncertainty from a deep ensemble drives an active-learning loop that screens large candidate pools in seconds and forwards only the most informative designs for full simulation. Benchmarked against Sentaurus Device on multi-fin tri-gate FinFETs, the surrogate reproduces the three drift-diffusion fields with sub-volt per-field RMSE and reaches a per-design throughput orders of magnitude higher than the full simulator. The advantage grows with device size: on large multi-fin arrays that are prohibitively slow to simulate directly, inference still completes in under a second per device, enabling Pareto-front exploration across device scales infeasible for direct TCAD sweeps.
发表机构
- University of Illinois Chicago（伊利诺伊大学芝加哥分校）
机构由 AI 辅助整理，请以论文原文为准。
