发表机构
Nanyang Technological University（南洋理工大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文针对双变量自行车码架构下多控托弗里门的映射难题，提出利用其二叉树结构的布局策略，结合外部魔术态工厂注入|CCZ>态，可减少模块间指令数并验证了编译电路的可行性。
AI 中文摘要
多控托弗里门（MCT门）是量子电路设计中的基本单元，应用于量子算术、密码分析和算法实现。作为高层逻辑操作，将MCT门高效分解为低层网表是数十年来的主要优化挑战。尽管双变量自行车（BB）码等新兴量子纠错码大幅降低了容错开销，但在模块化BB码架构上实现非克利福德电路会引入由模块间布线、工厂密度和布局决定的复杂编译瓶颈，因此MCT门到BB码架构的映射仍相对未被探索。本文中，我们通过将最优托弗里门深度的MCT分解（Dutta等人，《物理评论A》，2025年）映射到基于BB码的容错架构上，具体方法是从外部魔术态工厂直接注入|CCZ>态。我们引入了一种针对性布局策略，该策略利用MCT分解的二叉树结构将相互作用的子树共置，与朴素的顺序首次适应布局相比，此方法可将模块间指令数量最多减少16.02%。我们还评估了不同拓扑结构下工厂布局的影响，结果表明，与线性架构（Yoder等人，arXiv，2025年）相比，基于网格的布局可使模块间指令数量最多减少23.7%。最后，我们使用Qiskit社区提供的自行车数值工具（bicycle_numerics）的bicycle-ISA错误估计器，通过分析总执行错误和逻辑失败概率，验证了我们编译电路的实际可行性。
英文摘要
The multi-controlled Toffoli (MCT) gate is a fundamental primitive in quantum circuit design, with applications in quantum arithmetic, cryptanalysis, and algorithmic implementations. Being a high-level logical operation, the efficient decomposition of MCT gates into lower-level netlists has remained a major optimization challenge for decades. While emerging quantum error-correcting codes such as bivariate bicycle (BB) codes drastically reduce fault-tolerance overhead, realizing non-Clifford circuits on modular BB-code architectures introduces complex compilation bottlenecks governed by inter-module routing, factory density, and layout. Consequently, the mapping of MCT gates onto BB-code architectures remains relatively unexplored. In this paper, we overcome these challenges by mapping optimal-Toffoli-depth MCT decompositions (Dutta et al., PRA, 2025) onto BB-code-based fault-tolerant architectures via direct $\lvert \mathrm{CCZ} \rangle$ state injection from an external magic state factory. We introduce a targeted placement strategy that exploits the binary-tree structure of MCT decompositions to co-locate interacting subtrees. This approach reduces inter-module instruction counts by up to $\mathbf{16.02}\%$ compared to a naive sequential first-fit placement. We also evaluate the impact of factory placement across different topologies, demonstrating that grid-based layouts yield up to a $\mathbf{23.7}\%$ reduction in inter-module instructions relative to linear architectures (Yoder et al., arXiv, 2025). Finally, we validate the practical viability of our compiled circuits by analyzing aggregate execution errors and logical failure probabilities using the bicycle-ISA error estimator bicycle_numerics provided by the Qiskit community, https://github.com/qiskit-community/bicycle-architecture-compiler.
Comments7 pages, 3 figures
