发表机构
The Chinese University of Hong Kong; Tsinghua University（香港中文大学; 清华大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
针对电路表示学习受工业网表规模与时序动态建模缺陷制约的问题，提出DeepSeq3分层框架，结合双GNN架构与状态中心预训练，在大规模基准上实现BMC求解时间降18%且保证正确性。
AI 中文摘要
电路表示学习（CRL）为指导和优化核心电子设计自动化（EDA）任务提供了强大范式，但工业网表的巨大规模以及无法显式建模寄存器级时序动态的缺陷阻碍了其实际应用。为克服这些障碍，我们提出DeepSeq3，一种新型分层框架，将电路抽象为两级表示：由触发器（FF）划分的细粒度组合子图，以及对寄存器传输结构进行建模的高层超级节点图（SNG）。双图神经网络（GNN）架构在两级学习表示，捕捉局部布尔逻辑和全局状态转换。关键在于，我们引入以状态为中心的预训练方案，预测FF状态间的可达性，使模型具备对时序行为的深度理解。在大规模基准测试中，DeepSeq3方法展现出优异的可扩展性和更丰富的表示，将有界模型检查（BMC）求解时间减少18%，同时保证正确性。
英文摘要
Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the immense scale of industrial netlists and a failure to explicitly model register-level temporal dynamics. To overcome these barriers, we introduce DeepSeq3, a novel hierarchical framework that abstracts circuits into a two-level representation: fine-grained combinational subgraphs partitioned by flip-flops (FFs), and a high-level Super-Node Graph (SNG) that models the register-transfer structure. A dual Graph Neural Network (GNN) architecture learns representations at both levels, capturing local Boolean logic and global state transitions. Crucially, we introduce a state-centric pre-training scheme that predicts the reachability between FF states, endowing the model with a deep understanding of temporal behavior. Demonstrated on large-scale benchmarks, DeepSeq3's approach yields superior scalability and richer representations, reducing bounded model checking (BMC) solving time by 18% while guaranteeing correctness.
