一个开源的3D集成电路（3D-IC）测试用例基准套件
An Open-Source Benchmark Suite of 3D-IC Testcases
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中文总结 AI 辅助
针对现有基准无法覆盖3D-IC新物理设计挑战的问题，本文基于开源框架CATCH的小芯片案例研究，提出开源3D-IC基准套件，以推动该领域研究。
中文摘要 AI 辅助
过去三十年来，物理设计领域受益于标准化、公开可用的基准套件，这些套件支持可复现的评估，并推动了2D布局布线算法的显著进步。然而，3D异构集成技术的出现，包括硅通孔（TSV）、混合键合和基于小芯片（chiplet）的架构，带来了现有平面基准无法覆盖的新物理设计挑战。尽管已有多项3D-IC设计案例被报道，但能支持不同3D物理设计问题可复现评估的公开可用且可扩展的基准套件仍然有限。本文中，我们提出一个开源的3D-IC基准测试用例套件，该套件源自开源异构集成架构成本估算框架CATCH中具有代表性的基于小芯片的案例研究。所提出的基准套件提供可复用的虚拟小芯片模型，涵盖计算、内存、输入/输出（I/O）、模拟和衬底组件。每个测试用例都捕获了3D系统的基本物理设计特性，包括异构裸片集成、裸片间连接以及与工艺相关的设计约束。通过公开发布这些基准，我们旨在建立一个通用评估平台，推动整个社区在3D异构集成领域的研究进展。
英文摘要
The physical design community has benefited from standardized, publicly available benchmark suites, which have enabled reproducible evaluation and driven significant advances in 2D place-and-route algorithms over the past three decades. However, the emergence of 3D heterogeneous integration technologies, including through-silicon vias (TSVs), hybrid bonding, and chiplet-based architectures, has introduced new physical design challenges that are not captured by existing planar benchmarks. Although several 3D-IC design examples have been reported, publicly accessible and scalable benchmark suites that enable reproducible evaluation across different 3D physical design problems remain limited. In this paper, we present an open-source suite of 3D-IC benchmark testcases derived from representative chiplet-based case studies in CATCH, an open-source framework for estimating the cost of heterogeneous integration architectures. The proposed benchmark suite provides reusable virtual chiplet models covering compute, memory, I/O, analog, and substrate components. Each testcase captures essential physical design characteristics of 3D systems, including heterogeneous die integration, inter-die connectivity, and technology-dependent design constraints. By publicly releasing these benchmarks, we aim to establish a common evaluation platform and accelerate community-wide research progress in 3D heterogeneous integration.
