用于MKID读出的高隔离度宽带信道化器：基于RFSoC的自定义HLS实现
A high-isolation wideband channelizer for MKID readouts: a custom HLS implementation on RFSoC
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中文总结 AI 辅助
本研究针对MKID读出的频谱泄漏与scalloping损耗问题，在RFSoC上用自定义HLS实现高隔离度宽带信道化器，通过分路架构提升性能，验证了其低损耗特性并完成了MKID阵列的低温测试。
中文摘要 AI 辅助
本文介绍一种用于微波动力学电感探测器（Microwave Kinetic Inductance Detectors, MKIDs）的高性能信道化器，旨在通过50%重叠的多相滤波器组（polyphase filter bank, PFB）缓解频谱泄漏和 scalloping 损耗。该设计基于Xilinx Zynq UltraScale+ RFSoC ZCU111实现，采用自定义设计——主要在Vitis高层次综合（High-Level Synthesis, HLS）中完成，时间关键型输出串行器和粘合逻辑则用VHDL实现，可处理4.096 GSPS的输入流，每分支超采样率（super-sample rate, SSR）为16。我们的分路架构不依赖激进的512 MHz时钟和厂商IP核，而是并行计算延迟与非延迟多相分支，使信道化器的大部分模块工作在稳定的256 MHz，仅单个512 MHz子域局限于BRAM到FFT的部分。这种架构并行性支持深度为16抽头的原型滤波器，其抽头数是同类高速系统的两倍，大幅提升了信道隔离度。我们报告了实现重叠的重排序引擎的完整内部架构，其中包含两项现有技术未记录的实现隐患：影响HLS中状态切换的流水线级偏移，以及可重启设计的状态保持要求。2/1重叠的信道响应通过仿真验证——将临界采样信道化器的约3.9 dB scalloping 损耗在整个2 MHz信道范围内降至0.1 dB以下，并通过100音批量频率扫描进行系统表征；同时，该读出系统已在绝热去磁制冷机（adiabatic demagnetization refrigerator, ADR）中与MKID阵列一起低温运行，在完全黑暗环境中识别出单个谐振器。最终成果是一种资源高效、高隔离度的宽带频分复用读出基准方案。
英文摘要
We present a high-performance channelizer for Microwave Kinetic Inductance Detectors (MKIDs), designed to mitigate spectral leakage and scalloping loss through a 50% overlapping polyphase filter bank (PFB). The design is implemented on a Xilinx Zynq UltraScale+ RFSoC ZCU111 using a custom design - primarily in Vitis High-Level Synthesis (HLS), with the time-critical output serializer and glue logic in VHDL - that processes a 4.096 GSPS input stream with a per-branch super-sample rate (SSR) of 16. Rather than relying on aggressive 512 MHz clocking and vendor IP cores, our split-path architecture computes the delayed and non-delayed polyphase branches concurrently, so that the bulk of the channelizer operates at a robust 256 MHz while a single 512 MHz subdomain is confined to the BRAM-to-FFT section. This architectural parallelism enables a deep 16-tap prototype filter that doubles the filter depth of comparable high-speed systems and substantially improves channel isolation. We report the complete internal architecture of the reordering engine that implements the overlap, including two implementation hazards not documented in prior art: a pipeline-stage skew affecting state toggles in HLS, and the state-preservation requirements of a restartable design. The 2/1 overlapped channel response is validated in simulation - recovering the ~3.9 dB scalloping loss of a critically sampled channelizer to below 0.1 dB across the full 2 MHz channel - and characterized systematically with a 100-tone batch frequency sweep, while the parent readout system has been operated cryogenically with an MKID array in an adiabatic demagnetization refrigerator (ADR), identifying individual resonators in total darkness. The result is a resource-efficient, high-isolation benchmark for wideband frequency-division-multiplexed readouts.
