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FPGAgent:一种用于FPGA环境中自主HLS代码生成与验证的大语言模型辅助框架

FPGAgent: An LLM-Assisted Framework for Autonomous HLS Code Generation and Verification in FPGA Environments

Tianyu Wang, Wenjie Wang, Jianguo Yao, Haibing Guan, Xijun Li

arXiv 2608.23630首次发表:更新:

AI 中文总结

FPGAgent是首个经成熟基准验证的任务规范到可执行HLS生成的多智能体框架,可自主生成并验证FPGA的HLS代码,在HLS-Eval基准上可综合率等指标平均提升16.9%等,大幅提升了LLM生成HLS代码的实用性。

AI 中文摘要

大语言模型(LLM)在高级综合(HLS)代码生成方面已展现出巨大潜力,但现有多数方法仅验证仿真或综合结果。由于时序、布局与布线约束,通过仿真和综合的HLS代码仍可能无法在真实FPGA平台生成可部署、可运行的设计。此外,公开基准的缺乏使得许多评估只能在小型、自行整理的测试套件上进行。我们提出FPGAgent,这是一种专为真实FPGA环境设计的多智能体框架,用于自主HLS编码并具备端到端可执行性验证能力。据我们所知,FPGAgent是首个在成熟基准上经实验验证的、从任务规范到可执行HLS生成的框架。给定自然语言任务规范,FPGAgent会注入HLS特定知识,并采用进化搜索迭代推导可靠的HLS内核实现。随后,它生成C++验证程序以验证功能正确性,诊断潜在缺陷并指导针对性修复。最后,它合成主机代码用于在FPGA硬件上编译和板级执行。我们在HLS-Eval基准上对FPGAgent进行了全面评估,该基准包含跨多个领域的78个任务,并在真实FPGA平台上验证了板级可执行性。与现有基线相比,FPGAgent的可综合率平均提升16.9%,可执行性提升26.7%,功能正确性提升30.6%。这些结果表明,FPGAgent大幅提升了基于LLM的HLS生成的实际可用性,并证明了端到端验证的价值。

英文摘要

Large language models (LLMs) have shown substantial promise for high-level synthesis (HLS) code generation, but most existing approaches validate only simulation or synthesis results. Because of timing and place-and-route constraints, \emph{HLS code that passes simulation and synthesis may still fail to produce deployable, runnable designs on real FPGA platforms}. Moreover, the lack of public benchmarks has limited many evaluations to small, self-curated test suites. We propose FPGAgent, a multi-agent framework tailored to real FPGA environments for autonomous HLS coding with end-to-end executability validation. To the best of our knowledge, FPGAgent is \emph{the first task-specification-to-executable HLS generation framework experimentally validated on a well-established benchmark}. Given a natural-language task specification, FPGAgent injects HLS-specific knowledge and employs evolutionary search to iteratively derive reliable HLS kernel implementations. It then generates a C++ validation program to verify functional correctness, diagnoses potential defects, and guides targeted repairs. Finally, it synthesizes host code for compilation and board-level execution on FPGA hardware. We comprehensively evaluate FPGAgent with five established LLMs on HLS-Eval, a benchmark containing 78 tasks across multiple domains, and verify board-level executability on a real FPGA platform. Compared with existing baselines, FPGAgent improves the synthesizable rate by 16.9% on average, executability by 26.7%, and functional correctness by 30.6%. These results show that FPGAgent substantially improves the practical usability of LLM-based HLS generation and demonstrates the value of end-to-end validation.

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