AI 中文总结
该研究提出含101个FSM的基准测试集合，对比SYNTLOG与Vivado的综合性能，发现SYNTLOG在LUT数量、逻辑深度、运行时间上更优，且能完成Vivado无法处理的超大型电路综合验证。
AI 中文摘要
我们引入了一个经过整理的基准测试集合，包含101个有限状态机（FSM）描述，这些描述被划分为五个规模类别：小型、中型、大型、超大型、巨无霸型，覆盖的状态数量从数十到数千不等，输入和输出数量最多达数百个。利用这些基准，我们在综合（技术映射）层面，针对六种优化策略，将与架构无关的综合工具SYNTLOG与Xilinx Vivado进行了对比。我们对比了三个综合后参数：查找表（LUT）数量、逻辑级数和运行时间。在面积驱动模式下，SYNTLOG在所有规模下使用的LUT数量均显著少于Vivado的面积基准，减少幅度为45%至66%；其延迟驱动模式的逻辑深度同时比Vivado的默认综合模式更浅。SYNTLOG的综合过程包含嵌入式功能验证。SYNTLOG的运行时间比Vivado综合快一到两个数量级。该工具能在数分钟内完成每个超大型和巨无霸型电路的综合与验证，而Vivado在这些设计上运行数小时后仍无法完成。
英文摘要
We introduce a curated benchmark collection of \num{101} FSM descriptions organized into five size classes (\emph{small}, \emph{medium}, \emph{large}, \emph{huge}, \emph{super-huge}), spanning tens to thousands of states and up to hundreds of inputs and outputs. Using these benchmarks we compare an architecture-independent synthesis tool SYNTLOG against Xilinx Vivado at the synthesis (technology-mapping) level, under six optimization strategies. We compare three post-synthesis parameters: number of LUTs, number of logic levels, and runtime. SYNTLOG in area-driven mode uses substantially fewer LUTs than Vivado's area baseline at every size ($-45\%$ to $-66\%$), and its delay-driven mode is simultaneously shallower in logic depth than Vivado's default synthesis mode. SYNTLOG synthesis includes embedded functional validation. Runtime of SYNTLOG is faster by one to two orders of magnitude than Vivado synthesis. The proposed tool synthesizes and validates every \emph{huge} and \emph{super-huge} circuit in minutes, whereas Vivado fails to terminate on these designs after hours.
