AI 中文总结
该研究针对分布式容错超导量子计算，提出硬件协同设计与资源评估协议，以RSA-2048因式分解为基准，证明分布式架构资源开销适度且尺度不变，为可扩展的分布式容错超导量子计算提供可行方案。
AI 中文摘要
扩展容错超导量子计算机可能需要由多个可制造量子处理单元（QPU）构成的分布式架构。核心问题在于，与单片架构相比，噪声大且速度慢的片间操作是否会带来显著的时空开销或编排负担。为回答该问题，我们提出了基于硬件的架构协同设计，以及针对表面码（surface-code）模块化处理器的综合资源评估协议。该设计将片间延迟和噪声限制在模块边界，避免慢速、高噪声链路引发过高的时空开销或成为全局编排瓶颈。资源评估协议将硬件约束与电路级纠错性能整合到实用规模算法的成本估算中，实现对不同架构的可控评估。以RSA-2048因式分解作为高要求基准，我们在实验锚定参数和实际超导硬件约束下估算资源。与大型理想单片基线相比，所得分布式架构仅在量子比特数和执行时间上需要适度的额外资源开销。更重要的是，该开销在宽模块容量窗口内几乎是尺度不变的，将芯片尺寸与全局性能解耦。这种解耦使模块容量从精细调整的架构参数转变为灵活的工程自由度，允许芯片尺寸由可制造性和控制封装约束设定，而非架构精细调整。这些结果为分布式容错超导量子计算建立了可行路径，可在无过高资源增长或繁重编排负担的情况下实现扩展。
英文摘要
Scaling fault-tolerant superconducting quantum computers will likely require distributed architectures built from multiple manufacturable quantum processing units. A central question is whether noisy and slow inter-chip operations impose substantial spacetime overhead or orchestration burdens compared with monolithic architectures. To answer this question, we present a hardware-grounded architectural co-design together with a comprehensive resource-estimation protocol for surface-code-based modular processors. The design confines inter-chip latency and noise to module boundaries, preventing slow, noisy links from inducing prohibitive spacetime overhead or becoming a global orchestration bottleneck. The resource-estimation protocol integrates hardware constraints and circuit-level error-correction performance into utility-scale algorithmic cost estimates, enabling a controlled assessment of different architectures. Using RSA-2048 factorization as a demanding benchmark, we estimate resources under experimentally anchored parameters and realistic superconducting hardware constraints. Compared with a large, ideal monolithic baseline, the resulting distributed architecture requires only modest additional resource overhead in both qubit count and execution time. More importantly, the overhead is nearly scale-invariant across a broad module-capacity window, decoupling chip size from global performance. This decoupling turns module capacity from a finely tuned architectural parameter into a flexible engineering degree of freedom, allowing chip sizes to be set by manufacturability and control-packaging constraints rather than architectural fine-tuning. These results establish a viable route to distributed fault-tolerant superconducting quantum computation that scales without prohibitive resource growth or heavy orchestration burden.
