AI 中文总结
针对交换式CXL内存池的性能干扰问题，提出受CSFQ启发的MemChannel传输层，通过mchannel抽象及多项特有机制实现性能隔离，在多场景下验证了有效性。
AI 中文摘要
新兴的交换式CXL内存池系统虽具前景，但因主机核心与远程DIMM间并发内存流共享未受性能管控的数据路径，存在显著性能干扰。我们系统表征了基于XConn的Apollo CXL交换机的内存池设备，识别出三个问题：主机内争用、交换结构内拥塞及未管控的主机-远程DIMM交互。本文提出新的传输层MemChannel，提供mchannel抽象以管控竞争内存流间的端到端交换结构带宽，支持交换式CXL内存池的特定应用流量。核心思路是构建受Core-Stateless Fair Queueing（CSFQ）启发的发送方驱动、感知交换结构的传输协议，基于核心到CXL-DIMM的估计带宽可用性，为每个mchannel接纳适量CXL请求。为应对CXL特有特性，MemChannel引入基于时间的速率控制、主机侧接纳控制、跨主机记账、新型拥塞信号、基于流体模型的速率估计及基于延迟的链路容量调整。我们从零构建MemChannel，支持未修改的应用。对交换式内存池的评估从性能隔离、可扩展性及多租户视角验证了其有效性。
英文摘要
Emerging switched CXL memory pooling systems, albeit promising, suffer from significant performance interference due to the shared but performance-uncontrolled data path among concurrent memory streams between a host core and a remote DIMM. We systematically characterize a memory pooling appliance based on XConn's Apollo CXL switch and identify three issues: intra-host contention, in-fabric congestion, and unmanaged host-remote DIMM interaction. This paper presents a new transport layer, MemChannel, which provides the mchannel abstraction to manage end-to-end fabric bandwidth among competing memory flows and enable application-specific traffic for switched CXL memory pooling. Our key idea is to build a sender-driven, fabric-informed transport protocol, inspired by Core-Stateless Fair Queueing (CSFQ), that admits just the right amount of CXL requests to each mchannel based on the estimated core-to-CXL-DIMM bandwidth availability. To address CXL-induced idiosyncrasies, MemChannel introduces time-based rate control, host-side admission control, cross-host bookkeeping, new congestion signals, rate estimation based on the fluid model, and delay-based link-capacity adjustment. We build MemChannel from scratch and support unmodified applications. Evaluations over switched memory pooling demonstrate its effectiveness from performance-isolation, scalability, and multi-tenancy perspectives.
