2%带宽内，模式乘法法对阵列波导缝隙平面阵列的旁瓣电平低估了1.1至2.8 dB
Pattern Multiplication Underestimates the Sidelobe Level of a Planar Slotted-Waveguide Array by 1.1 to 2.8 dB Across a 2% Band
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中文总结 AI 辅助
该研究对比了波导缝隙阵列设计的模式乘法快捷法与全波解，发现其在2%带宽内低估旁瓣电平1.1至2.8 dB，误差源于边缘单元，且Stevenson电导存在恒定高估。
中文摘要 AI 辅助
对波导缝隙阵列设计中的标准快捷方法——求解单个辐射臂，将其嵌入方向图乘以目标口径分布的阵列因子，并将乘积作为阵列方向图——与相同金属结构的全波解进行了对比测试。针对WR-90中合成的16×16缝隙平面阵列，其采用-30 dB泰勒激励，该快捷方法在设计频率下低估了横平面旁瓣电平1.06 dB，在2%带宽边缘分别低估2.22 dB和2.84 dB，差值达1.78 dB，大于中频本身的误差。所有旁瓣数值均包含±0.11 dB的网格 spread，该 spread 来自对生产几何结构的收敛性研究。误差为有符号值，在设计余量最小的带宽边缘最为严重，且当口径从8个臂加倍至16个臂时，误差仅从1.58 dB降至1.06 dB，这表明边缘单元是误差来源。该阵列通过13点单缝隙全波校准实现可分析性：在设计偏移范围内，谐振长度的手册闭式公式偏移3.9微米，而测量偏移143.9微米，且Stevenson电导被高估了近恒定的5.16%。
英文摘要
The standard shortcut in slotted-waveguide array design -- solve one radiating stick, multiply its embedded pattern by the array factor of the intended aperture distribution, and accept the product as the array pattern -- is tested against a full-wave solution of the same metal. For a 16x16-slot planar array in WR-90 synthesised to a -30 dB Taylor illumination, the shortcut underestimates the transverse-plane sidelobe level by 1.06 dB at the design frequency and by 2.22 and 2.84 dB at the edges of a 2% band: a spread of 1.78 dB, larger than the mid-band error itself. Every sidelobe figure carries +/-0.11 dB of mesh spread from a convergence study on the production geometry. The error is signed, is worst at the band edges where the design has least margin, and falls only from 1.58 dB to 1.06 dB when the aperture is doubled from eight sticks to sixteen, which identifies the edge elements as its source. The array was made analysable by a thirteen-point single-slot full-wave calibration: over the design's offset range the handbook closed form for resonant length moves 3.9 micrometres where the measurement moves 143.9 micrometres, and Stevenson's conductance is shown to overestimate by a nearly constant 5.16%.
