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扩展规模还是扩展输出:评估模块化超导量子处理器上编译逻辑电路的时空成本

To Scale Up or To Scale Out: Evaluating Space-Time Costs of Compiled Logical Circuits on Modular Superconducting Quantum Processors

Nikiforos Paraskevopoulos, Sebastian de Bone, Mick Christophersen, Simon Storz, A. Mert Bozkurt, Arno Bargerbos, Sebastian Feld

arXiv 2608.20462首次发表:更新:

AI 中文总结

该研究针对模块化超导量子处理器,通过定量压力测试对比基于小芯片和分布式两种扩展策略的时空成本,发现分布式架构存在指数级性能损失,损失源于噪声或连接性主导的不同机制。

AI 中文摘要

模块化集成已成为将超导量子处理单元(QPU)扩展至超出制造良率和物理尺寸限制的主要途径。目前,有两种主要策略引领这一努力:效仿GPU架构和AI基础设施中的“扩展规模”(Scaling Up)与“扩展输出”(Scaling Out)方法,分别是基于小芯片(chiplet)的扩展,其保留了密集的连接性和高门保真度,但代价是工程复杂性;以及分布式架构,其将系统扩展与单片QPU的进步解耦,但代价是连接性更稀疏和互连质量更低。为评估这些方法,我们引入了一种定量压力测试,该测试使用表面码方案测量随机逻辑纠缠操作的密集工作负载的执行成本。我们使用专用编译器计算随着网络节点数量增加的时空成本,分析在各种表面码距离、贝尔态保真度和贝尔对生成时间下的这种扩展行为。我们发现,在所有模拟中,与有效单片架构相比,分布式架构会产生高达指数级的时空性能损失。我们的结果还表明,随着网络的增长,这种损失表现为两种不同的扩展机制:受贝尔态保真度和生成率不足限制的噪声主导机制,以及受格点手术路由拥塞限制的连接性主导机制。

英文摘要

Modular integration has emerged as the main pathway for scaling superconducting quantum processing units (QPUs) beyond the constraints of fabrication yield and physical footprint. Currently, two primary strategies lead this effort. Mirroring the "Scaling Up" and "Scaling Out" approaches in GPU architectures and AI infrastructures, these are: chiplet-based scaling, which preserves dense connectivity and high gate fidelity at the expense of engineering complexity, and distributed architectures, which decouple system scaling from monolithic QPU advancements at the expense of sparser connectivity and lower interconnect quality. To evaluate these approaches, we introduce a quantitative stress test measuring the execution cost of a dense workload of random logical entangling operations using a surface code scheme. Using a dedicated compiler, we compute the space-time cost as the number of network nodes increases, analysing this scaling behaviour across various surface code distances, Bell-state fidelities, and Bell-pair generation times. We find that distributed architectures incur an up to exponential space-time performance penalty compared to an effectively monolithic architecture across all simulations. Our results also show that as the network grows, this penalty manifests in two distinct scaling regimes: a noise-dominated regime constrained by insufficient Bell-state fidelity and generation rates, and a connectivity-dominated regime bottlenecked by lattice-surgery routing congestion.

Comments18 pages, 7 figures

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