AI 中文总结
针对VLSI电路电压跌落限制工作频率的问题，采用IHP 130 nm工艺实现快速全数字自适应校正电路并在测试芯片上验证其功能。
AI 中文摘要
出于节能目的而缩小保护带的趋势，使得电压跌落成为当今超大规模集成电路（VLSI）工作频率的关键限制因素。动态调整时钟频率带来了检测和存储电压跌落存在的器件中的亚稳态挑战。我们采用IHP 130 nm工艺实现了一种用于对电压跌落做出自适应响应的快速全数字电路，该设计的详细说明载于配套论文中，我们在测试芯片上实验验证了该设计的功能。
英文摘要
Due to the trend towards minimizing guard bands for energy saving purposes, voltage droops are a key limiting factor for the operational frequency of today's VLSI circuits. Adapting clock frequencies dynamically presents the challenge of metastability in the device that detects and stores the existence of voltage droops. We present an implementation of a fast all-digital circuit for adaptive response to droops using the IHP 130 nm process. The description of the design is presented in an accompanying paper. We experimentally validate the functionality of the design on a test chip.
CommentsThis article reports on the experimental validation of the design proposed in https://arxiv.org/abs/2501.18843
