基于堆叠集成框架的异构内存IP中MBIST面积与测试时间的自动化估算
Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
浏览论文内容
中文总结 AI 辅助
本研究提出堆叠集成框架，基于RTL参数直接预测异构内存IP的MBIST面积与测试时间，准确率优于基线方法，可快速估算MBIST开销以支持高效设计决策。
中文摘要 AI 辅助
嵌入式存储器在现代片上系统（SoC）设计中占据很大比例，尤其在人工智能、边缘计算等高性能应用领域。存储器内置自测试（MBIST）通常用于保障存储器可靠性，但会引入额外的面积与测试时间开销。在设计规划阶段，准确估算这些开销十分重要，而传统方法依赖完整的寄存器传输级（RTL）综合与测试向量生成，速度慢且资源密集。本研究提出一种监督学习框架，无需综合即可直接从RTL级设计参数预测MBIST面积与测试时间。通过Synopsys Design Compiler与英特尔增强型MBIST工具MINT生成了4470个面积样本、624个测试时间样本的数据集，输入特征包括存储器数量、字宽、地址深度、端口配置及时钟域。对于面积预测，特征经多项式展开、对数变换与缩放后，输入至由XGBoost、LightGBM及以梯度提升为元学习器的神经网络组成的堆叠集成模型；对于测试时间，将XGBoost与LightGBM结合岭回归，通过100次试验的Optuna搜索调优超参数。这些模型在±10%误差范围内，面积预测准确率达90.68%，测试时间预测准确率达96.80%，较基线方法分别提升8.53%与48.80%。结果表明，该方法可实现MBIST开销的更快估算，为内存IP开发提供更高效的设计决策支持。
英文摘要
Embedded memories occupy a large portion of modern System-on-Chip (SoC) designs, especially in high-performance applications such as artificial intelligence and edge computing. Memory Built-In Self-Test (MBIST) is commonly used to ensure memory reliability, but it introduces additional area and test time overhead. Accurate early estimation of these overheads is important during design planning, yet conventional methods rely on full Register Transfer Level (RTL) synthesis and test pattern generation, which are slow and resource-intensive. This study proposes a supervised learning framework that predicts MBIST area and test time directly from RTL-level design parameters without synthesis. A dataset of 4,470 samples for area and 624 for test time was generated using Synopsys Design Compiler and MINT, an Intel-enhanced MBIST tool. Input features include memory count, word width, address depth, port configuration, and clock domains. For area prediction, the features are processed through polynomial expansion, log transformation, and scaling, followed by a stacked ensemble model using XGBoost, LightGBM, and a Neural Network with Gradient Boosting as the meta-learner. For test time, XGBoost and LightGBM are combined using Ridge Regression, with hyperparameters tuned through a 100-trial Optuna search. The models achieved 90.68% accuracy for area and 96.80% for test time within a +/-10% margin, improving over baseline methods by 8.53% and 48.80% respectively. The results show that this approach enables faster estimation of MBIST costs and supports more efficient design decisions in memory IP development.
