AI 中文总结
该研究针对ESA NewAthena卫星WFI的DEPFET探测器读出需求，迭代优化VERITAS架构得到2.3.1版本，通过多步骤测试表征其性能并与旧版对比，提升了系统多方面特性。
AI 中文摘要
VERITAS 2.3.1是基于集成梯形模拟整形器的通用读出（VERITAS）集成电路架构的下一代迭代版本，用于欧洲空间局（ESA）NewAthena X射线卫星的宽场成像仪（WFI）中耗尽型场效应晶体管（DEPFET）探测器的高速、低噪声读出。VERITAS 2.3已实现每次读出2.5微秒的短处理时间和约3个电子等效噪声电荷（e- ENC RMS）的系统噪声目标，VERITAS 2.3.1版本在保留已验证的VERITAS架构的基础上，通过额外功能、现有模拟与数字模块的针对性优化，以及精细化布线以减少寄生效应，提升了瞬态特性、串扰、可制造性和可靠性。VERITAS 2.3.1的功能与特性分两步表征：第一步采用专用的专用集成电路（ASIC）测试装置；第二步采用全尺寸模块测试装置，集成DEPFET传感器与读出电子设备，在真空及任务模拟温度下开展测试。本文介绍VERITAS 2.3.1的设计更新与实现细节，将其实测性能与VERITAS 2.3进行对比，并讨论新增功能、模块级优化及布线改进对整体系统性能的影响。
英文摘要
VERITAS 2.3.1 is the next iteration of the VErsatile Readout based on Integrated Trapezoidal Analogue Shapers (VERITAS) integrated circuit (IC) architecture for high-speed, low-noise readout of DEPleted Field Effect Transistor (DEPFET) detectors in the Wide Field Imager (WFI) on ESA's NewAthena X-ray satellite. Building on VERITAS 2.3, which demonstrated a short processing time of 2.5 us per readout and a system noise target of about 3 e- ENC RMS, the VERITAS 2.3.1 revision has been improved with additional features and targeted optimisations of existing analogue and digital blocks, alongside refined layout routing to reduce parasitic effects, to improve transient behavior, cross talk, manufacturability, and reliability while preserving the proven VERITAS architecture. The functionality and performance of VERITAS 2.3.1 was characterised in two steps. First by using a dedicated application specific integrated circuit (ASIC) only test setup. Second, a full scale module test setup is used, with integrated DEPFET sensors and readout electronics, under vacuum and at mission like temperatures. This paper presents the design updates and implementation details of the VERITAS 2.3.1, compares its measured performance to that of VERITAS 2.3, and discusses the impact of the added features, block-level optimisations, and routing improvements on overall system performance.
