面向RISC-V系统的FPGA生命周期管理
FPGA Lifecycle Management for RISC-V Systems
AI总结：
针对RISC-V系统缺乏厂商中立FPGA生命周期管理模型的问题，提出基于Linux能力的主机无关控制平面架构，在Zynq-7000 SoC上实现原型，为 fleet级FPGA管理提供可移植基础。
AI中文摘要：
FPGA生命周期管理目前仍与专有工具链和主机架构绑定，RISC-V缺乏厂商中立的可扩展比特流部署模型。本文提出一种与主机无关的控制平面架构，通过利用标准Linux能力将生命周期管理转移到操作系统层，从而将部署与特定ISA和厂商栈解耦。这使支持Linux的RISC-V处理器可作为异构FPGA系统中的控制主机。该架构在Zynq-7000 SoC上实现原型，且可推广到RISC-V平台，为 fleet级FPGA管理提供可移植基础。
英文摘要：
FPGA lifecycle management remains tied to proprietary toolchains and host architectures, leaving RISC-V without a vendor-neutral model for scalable bitstream deployment. A host-agnostic control-plane architecture is presented that shifts lifecycle management to the operating-system layer by leveraging standard Linux capabilities, thereby decoupling deployment from specific ISAs and vendor stacks. This enables Linux-capable RISC-V processors to serve as control hosts in heterogeneous FPGA systems. Prototyped on a Zynq-7000 SoC and generalizable to RISC-V platforms, the architecture provides a portable foundation for fleet-scale FPGA management.
