开源集成电路设计中用于轻量级预布线延迟估计的混合机器学习方法
Hybrid ML for Lightweight Pre-Route Delay Estimation in Open-Source IC Design
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中文总结 AI 辅助
本研究针对开源IC设计预布线延迟估计难题，提出结合决策树与线性回归的混合轻量级ML方法，其误差较OpenLane降低80%，兼具高准确率、小体积、快速度与高可解释性。
中文摘要 AI 辅助
静态时序分析（STA）是数字集成电路设计流程中的关键步骤，但在物理设计信息有限时，获取准确的延迟估计颇具挑战。为此，本研究提出一种混合轻量级机器学习（ML）方法，将决策树与线性回归相结合，以改进开源RTL至GDSII工具OpenLane生成的预布线延迟估计。该模型与OpenLane的估计相比，误差降低80%；即便不使用OpenLane特定参数，仍实现71%的性能提升。总体而言，该方法为传统延迟传播技术及更复杂的机器学习模型提供了替代方案，不仅准确，且规模小300倍以上、速度快2倍，可解释性更高。
英文摘要
Static Timing Analysis (STA) is a critical step in the design flow of digital integrated circuits, however, obtaining accurate delay estimations can represent a challenge when limited information regarding physical design is available. In response, this work presents a hybrid and light-weight machine learning (ML) based approach that combines a decision tree with linear regression to improve pre-routing delay estimations generated by the open-source RTL-to-GDSII tool OpenLane. The proposed model achieves an 80\% reduction in error compared to OpenLane's estimates, demonstrates a 71\% improvement even without utilizing OpenLane-specific parameters. Overall, this method offers an alternative to traditional delay propagation techniques and more complex machine learning models that is not only accurate, but is also over 300 times smaller, 2 times faster and offers a higher explainability.
发表机构
- Universidad de Costa Rica（哥斯达黎加大学）
机构由 AI 辅助整理，请以论文原文为准。
