RENESIS：基于不可逆网表的绝热逻辑的能量感知综合
RENESIS: Energy-Aware Synthesis of Adiabatic Logic from Irreversible Netlists
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中文总结 AI 辅助
Renesis是一款自动化综合工具，可将不可逆网表转化为能量优化的绝热电路，经等价性检查，在多组电路上实现能量改进，相关资源以开源发布。
中文摘要 AI 辅助
我们描述了Renesis，这是一种自动化综合工具，它接受普通的不可逆网表并生成经过验证的、技术映射的能量恢复（绝热）电路，使用能量而非面积或延迟作为优化标准。Renesis用矢量空间公式对网表进行建模，该公式将模拟和验证扫描表示为正向和反向遍历，其成本与电路组件的数量呈线性关系。这些遍历会在账本中填充数据标签，这些标签以其天然的Rényi阶表征切换、擦除和可观测性信息。输出是一个逻辑可逆电路，映射到八个能量恢复系列之一，并报告相关参数。此处将可逆性视为电路级要求而非热力学要求。当绝热门擦除信息时，惩罚不是$k_B T \ln 2$，而是完全非绝热的$CV^2$放电，这与该电路类型旨在恢复的切换能量相当。每次综合转换都经过等价性检查，并且必须改进两个报告的成本表之一，一个无上限，一个在系列可实现性边界之后，同时不恶化其他成本表，才能被接受。在包含20个电路的开发集上，可选的重新综合过程改进了14个电路。在保留的20个电路中，19个中的15个得到了改进，最佳臂中位数为默认能量的0.91。一个经过认证的最优间隙程序计算了综合电路与工具自身搜索空间可证明下限之间的距离。一个器件级SPICE deck在参考系列上复现了工具的每周期能量数据。该工具、基准网表、验证程序以及每个报告数字背后的运行记录都作为开源发布。
英文摘要
We describe Renesis, an automated synthesis tool that accepts an ordinary irreversible netlist and produces a verified, technology-mapped energy-recovery (adiabatic) circuit, using energy rather than area or delay as the optimization criterion. Renesis models the netlist with a vector-space formulation that expresses simulation and justification sweeps as forward and reverse traversals whose cost is linear in the number of circuit components. The traversals populate ledgers with data tags that characterize switching, erasure, and observability information at their natural Rényi orders. The output is a logically reversible circuit mapped to one of eight energy-recovery families, with the associated parameters reported. Reversibility is treated here as a circuit-level requirement rather than a thermodynamic one. When an adiabatic gate erases information the penalty is not $k_B T \ln 2$ but a full non-adiabatic $CV^2$ discharge, which is comparable to the switching energy the circuit style exists to recover. Every synthesis transformation is equivalence-checked, and it must improve one of two reported cost tables, one uncapped and one after a series-realizability bound, while worsening neither before it is accepted. Across a twenty-circuit development set, optional re-synthesis passes improve fourteen circuits. On a held-out set of twenty circuits, fifteen of nineteen are improved, with a best-arm median of $0.91$ of the default energy. A certified optimality-gap program computes the distance between the synthesized circuits and the provable floor of the tool's own search space. A device-level SPICE deck reproduces the tool's per-cycle energy figures on the reference family. The tool, the benchmark netlists, the validation procedure, and the run records behind every reported number are released as open source.
