AaLLM：基于大语言模型的从拓扑生成到尺寸确定的端到端模拟电路设计框架

中文摘要 AI 辅助

模拟电路设计是一个耗时、迭代的过程，发生在非线性且高维的设计空间中，极大依赖于专家的直觉。在近期的发展中，大语言模型（LLM）通过将自然语言推理引入电路设计任务，提供了一种有前景的方法。大多数基于LLM的传统方法提供碎片化的解决方案，仅专注于尺寸确定或拓扑生成，这些方法需要手动添加特定技术知识，效率低下且在电路尺寸确定过程中容易产生幻觉。此外，满足不同规格指标时的固有权衡使得当前方法迭代且繁琐，另一个缺点是无法创建创新拓扑，由于依赖传统拓扑，可能导致设计次优。在本文中，我们提出AaLLM，这是一个开源的端到端多智能体LLM工作流，以用户规格指标作为输入，输出合适的网表，涵盖拓扑生成和电路尺寸确定。AaLLM自动从研究论文和教材创建相关知识库，以应对繁琐的手动数据收集；实现检索增强生成（RAG）模型，利用该知识库模拟电路设计专业知识。此外，AaLLM采用新颖的三智能体反馈系统，包括确定电路元件值的设计者、审查这些值的批评者，以及通过在另外两个智能体之间进行仲裁来最小化电路尺寸确定迭代次数的评估者。AaLLM生成的创新拓扑达到了与已知拓扑相当的品质因数（FoM），对于某些电路，品质因数可高达3倍。在多种电路拓扑上的测试结果显示，与最先进（SOTA）的多智能体LLM流水线相比，AaLLM在推理阶段的SPICE调用次数减少了3倍至4.5倍；与现有方法相比，挂钟时间减少了40倍。

英文摘要

Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition. Among recent developments, LLMs have introduced a promising approach by bringing natural language reasoning to circuit design tasks. The majority of conventional LLM-based approaches provide fragmented solutions that focus either only on sizing or topology generation. These methods require adding specific technical knowledge manually, which is inefficient and prone to hallucinations during circuit sizing. Moreover, the inherent trade-off in meeting different specs makes current approaches iterative and tedious. Another shortcoming is the inability to create innovative topologies, which may lead to sub-optimal designs due to reliance on conventional topologies. In this paper, we present AaLLM, an open-source end-to-end multi-agent LLM workflow that takes user specs as input and outputs the appropriate netlist, encompassing both topology generation and circuit sizing. AaLLM automates the creation of a relevant knowledge base from research papers and textbooks to combat tedious manual data collection. A RAG model is implemented to emulate circuit design expertise using this knowledge base. Moreover, AaLLM uses a novel tri-agent feedback system comprising a Designer that determines circuit component values, a Critic that scrutinizes these values, and an Evaluator that minimizes circuit sizing iterations by arbitrating between the other two agents. AaLLM-generated novel topologies achieve a figure of merit (FoM) comparable to that of known topologies, and up to 3x higher for certain circuits. Testing on several circuit topologies, our results show a 3x - 4.5x decrease in the number of SPICE calls at inference when compared to SOTA multi-agent LLM pipelines. The results also show a 40x decrease in wall-clock time compared to existing approaches.

发表机构

• University of Utah（犹他大学）

机构由 AI 辅助整理，请以论文原文为准。