AI 中文总结
本研究采用22nm FDSOI技术实现前馈泄漏抑制逻辑（FLSL），可显著降低始终在线（AO）电路的泄漏功率，相比HVT和UHVT CMOS设计分别降低达9.8倍和1.83倍。
AI 中文摘要
可穿戴设备与物联网边缘设备上实时应用的日益部署，加剧了对满足严格时序和能量约束的高能效、高性能系统的需求。事件驱动架构利用实时性的稀疏性，通过采用始终在线（AO）域监测输入，仅在相关事件发生时激活高性能（HP）域，进一步提升系统能效。然而，对于低占空比应用，能量瓶颈转向AO域，其中泄漏功率占总功耗的主导地位。为缓解此问题，AO电路通常采用高阈值电压（HVT）或超高阈值电压（UHVT）晶体管实现，从而避免对工艺、电压和温度（PVT）变化高度敏感的亚阈值和近阈值操作。在此背景下，前馈泄漏抑制逻辑（FLSL）近期成为有前景的候选方案，相比传统电路可降低泄漏。但此前研究报告，在90nm以下工艺节点中，FLSL的泄漏性能显著下降，主要源于栅极和结泄漏电流的增加。FDSOI技术具备有效抑制结泄漏的能力，为克服此限制并恢复FLSL在先进节点的效率提供了可能。因此，本研究展示，在22nm FDSOI工艺中实现的FLSL，与最先进的超低功耗CMOS设计相比，可显著降低具有低频输入的小型AO电路的能耗。对FIR滤波器和AES加密核的硅测量显示，与等效HVT和UHVT CMOS实现相比，其工作电压降低，泄漏功率分别降低达9.8倍和1.83倍。
英文摘要
The growing deployment of real-time applications on wearable and Internet of Things (IoT) edge devices has intensified the need for energy-efficient, high-performance systems that meet stringent timing and energy constraints. Events-driven architectures leverage the sparsity of real-time to further improve system energy efficiency by employing an always-on (AO) domain to monitor inputs and activate a high-performance (HP) domain only when relevant events occur. However, for low-duty-cycle applications, the energy bottleneck shifts toward the AO domain, where leakage power dominates overall consumption. To mitigate this issue, AO circuits are typically implemented using high voltage threshold (HVT) or ultra-high voltage threshold (UHVT) transistors, thereby avoiding sub- and near-threshold operation, which is highly sensitive to process, voltage, and temperature (PVT) variations. In this context, feedforward leakage suppression logic (FLSL) has recently emerged as a promising candidate, offering reduced leakage compared to conventional. However, previous studies report a significant degradation in FLSL leakage performance in technology nodes below 90 nm, primarily due to increased gate and junction leakage currents. FDSOI technology, with its ability to effectively suppress junction leakage, provides an opportunity to overcome this limitation and restore FLSL efficiency in advanced nodes. Therefore, we demonstrate in this work that FLSL implemented in a 22 nm FDSOI technology can significantly reduce the energy consumption of small AO circuits with low-frequency inputs compared to state-of-the-art ultra-low-power CMOS designs. Silicon measurements on an FIR filter and an AES cryptographic core show reduced operating voltage and up to 9.8 x and 1.83 x reductions in leakage power compared to equivalent HVT and UHVT CMOS implementations, respectively.
